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EBE25UD6ABFA

Elpida Memory
Part Number EBE25UD6ABFA
Manufacturer Elpida Memory
Description 256MB Unbuffered DDR2 SDRAM DIMM
Published Mar 21, 2010
Detailed Description PRELIMINARY DATA SHEET www.DataSheet4U.com 256MB Unbuffered DDR2 SDRAM DIMM EBE25UD6ABFA (32M words × 64 bits, 1 Rank)...
Datasheet PDF File EBE25UD6ABFA PDF File

EBE25UD6ABFA
EBE25UD6ABFA

Overview
PRELIMINARY DATA SHEET www.
DataSheet4U.
com 256MB Unbuffered DDR2 SDRAM DIMM EBE25UD6ABFA (32M words × 64 bits, 1 Rank) Description The EBE25UD6ABFA is 32M words × 64 bits, 1 rank DDR2 SDRAM unbuffered module, mounting 4 pieces of 512M bits DDR2 SDRAM sealed in FBGA package.
Read and write operations are performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 4 bits prefetch-pipelined architecture.
Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design.
By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable.
This module provides high density mounting without utilizing surface mount technology.
Decoupling capacitors are mounted beside each FBGA on the module board.
Note: Do not push the components or drop the modules in order to avoid mechanical defects, which may result in electrical defects.
Features • 240-pin socket type dual in line memory module (DIMM)  PCB height: 30.
0mm  Lead pitch: 1.
0mm  Lead-free • 1.
8V power supply • Data rate: 533Mbps/400Mbps (max.
) • 1.
8V (SSTL_18 compatible) I/O • Double-data-rate architecture: two data transfers per clock cycle • Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver • DQS is edge aligned with data for READs: centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS • Four internal banks for concurrent operation (components) • Data mask (DM) for write data • Burst lengths: 4, 8 • /CAS Latency (CL): 3, 4, 5 • Auto precharge operation for each burst access • Auto refresh and self refresh modes • 7.
8µs average periodic refresh interval • Posted CAS by programmable additive latency for better command and data bus efficiency • Off...


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