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EBE51RD8ABFA Datasheet PDF


Part Number EBE51RD8ABFA
Manufacturer Elpida Memory
Title 512MB Registered DDR2 SDRAM DIMM
Description The EBE51RD8ABFA is a 64M words × 72 bits, 1 rank DDR2 SDRAM Module, mounting 9 pieces of DDR2 SDRAM sealed in FBGA (µBGA) package. Read and writ...
Features
• 240-pin socket type dual in line memory module (DIMM)  PCB height: 30.0mm  Lead pitch: 1.0mm  Lead-free
• 1.8V power supply
• Data rate: 533Mbps/400Mbps (max.)
• 1.8 V (SSTL_18 compatible) I/O
• Double-data-rate architecture: two data transfers per clock cycle
• Bi-directional, data strobe (DQS...

File Size 208.69KB
Datasheet EBE51RD8ABFA PDF File








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EBE51RD8AEFA : The EBE51RD8AEFA is a 64M words × 72 bits, 1 rank DDR2 SDRAM Module, mounting 9 pieces of DDR2 SDRAM sealed in FBGA (µBGA) package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 4bits prefetch-pipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each FBGA (µBGA) on the module board. Note: Do not push t.

EBE51RD8AEFA-6 : The EBE51RD8AEFA is a 64M words × 72 bits, 1 rank DDR2 SDRAM Module, mounting 9 pieces of DDR2 SDRAM sealed in FBGA package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 4bits prefetch-pipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each FBGA on the module board. Note: Do not push the components o.

EBE51RD8AGFA : The EBE51RD8AGFA is a 64M words × 72 bits, 1 rank DDR2 SDRAM Module, mounting 9 pieces of DDR2 SDRAM sealed in FBGA (µBGA) package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 4bits prefetch-pipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each FBGA (µBGA) on the module board. Note: Do not push t.

EBE51RD8AJFA : Pin name A0 to A13 A10 (AP) BA0, BA1 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /CS0 CKE0 CK0 /CK0 DQS0 to DQS17, /DQS0 to /DQS17 DM0 to DM8 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS ODT0 /RESET NC Par_In* 2 2 www.DataSheet4U.com Function Address input Row address Column address Auto precharge Bank select address Data input/output Check bit (Data input/output) Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Input reference voltage Ground ODT control .




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