DatasheetsPDF.com

EBE51RD8AEFA

Part Number	EBE51RD8AEFA
Manufacturer	Elpida Memory
Description	512MB Registered DDR2 SDRAM DIMM
Published	Mar 21, 2010
Detailed Description	DATA SHEET www.DataSheet4U.com 512MB Registered DDR2 SDRAM DIMM EBE51RD8AEFA (64M words × 72 bits, 1 Rank) Description...
Datasheet	EBE51RD8AEFA PDF File

Overview

DATA SHEET www.
DataSheet4U.
com 512MB Registered DDR2 SDRAM DIMM EBE51RD8AEFA (64M words × 72 bits, 1 Rank) Description The EBE51RD8AEFA is a 64M words × 72 bits, 1 rank DDR2 SDRAM Module, mounting 9 pieces of DDR2 SDRAM sealed in FBGA (µBGA) package.
Read and write operations are performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 4bits prefetch-pipelined architecture.
Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design.
By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable.
This module provides high density mounting without utilizing surface mount technology.
Decoupling capacitors are mounted beside each FBGA (µBGA) on the module board.
Note: Do not push the components or drop the modules in order to avoid mechanical defects, which may result in electrical defects.
Features • 240-pin socket type dual in line memory module (DIMM)  PCB height: 30.
0mm  Lead pitch: 1.
0mm  Lead-free • Power supply: VDD, VDDQ = 1.
8V ± 0.
1V • Data rate: 533Mbps/400Mbps (max.
) • SSTL_18 compatible I/O • Double-data-rate architecture: two data transfers per clock cycle • Bi-directional, data strobe (DQS and /DQS) is transmitted /received with data, to be used in capturing data at the receiver • DQS is edge aligned with data for READs; center aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data referenced to both edges of DQS • Four internal banks for concurrent operation (components) • Data mask (DM) for write data • Burst length: 4, 8 • /CAS latency (CL): 3, 4, 5 • Auto precharge option for each burst access • Auto refresh and self refresh modes • Average refresh period  7.
8µs at 0°C ≤ TC ≤ +85°C  3.
9µs at +85°C < TC ≤ +95°C • Posted CAS by programmable additive latency for better command and data bus efficien...

Similar Datasheet

EBE51RD8AEFA 512MB Registered DDR2 SDRAM DIMM - Elpida Memory
EBE51RD8AEFA-6 512MB Registered DDR2 SDRAM DIMM - Elpida Memory

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)