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IS61NVP102436A

Part Number	IS61NVP102436A
Manufacturer	Integrated Silicon Solution
Description	36Mb STATE BUS SRAM
Published	Mar 24, 2010
Detailed Description	IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A 1Mb x 36 and 2Mb x 18 36Mb, PIPELINE 'NO WAIT' STATE BUS SRA...
Datasheet	IS61NVP102436A PDF File

Overview

IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A 1Mb x 36 and 2Mb x 18 36Mb, PIPELINE 'NO WAIT' STATE BUS SRAM FEBRUARY 2012 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP package • Power supply: NVP: VDD 2.
5V (± 5%), VDDQ 2.
5V (± 5%) NLP: VDD 3.
3V (± 5%), VDDQ 3.
3V/2.
5V (± 5%) • Industrial temperature available • Lead-free available DESCRIPTION The 36 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications.
They are organized as 1M words by 36 bits and 2M words by 18 bits, fabricated with ISSI's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read.
This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input.
Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH.
In this state the internal device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the ADV input.
When the ADV is HIGH the internal burst counter is incremented.
New external addresses can be loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW.
Separate byte enab...

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