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ICSSSTVA16859B Datasheet PDF

Integrated Circuit Systems
Part Number ICSSSTVA16859B
Manufacturer Integrated Circuit Systems
Title DDR 13-Bit to 26-Bit Registered Buffer
Description The 13-bit-to-26-bit ICSSSTVA16859B is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels, except for the LVCMOS...
Features
• Differential clock signals
• Meets SSTL_2 signal data
• Supports SSTL_2 class I specifications on outputs
• Low-voltage operation - VDD = 2.3V to 2.7V
• Available in 64 pin TSSOP and 56 pin MLF packages
• Exceeds SSTVN16859 performance Pin Configurations Q13A Q12A Q11A Q10A Q9A VDDQ GND Q8A Q7A ...

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ICSSSTVA16859B ICSSSTVA16859B ICSSSTVA16859B




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ICSSSTVA16857 : The 14-bit ICSSSTVA16857 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels, except for the LVCMOS RESET# input. Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTVA16857 supports low-power standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset to the logic “Low” state, and all input receivers, data (D) and clock (CLK/CLK#) are switche.

ICSSSTVA16859C : The 13-bit-to-26-bit ICSSSTVA16859C is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels, except for the LVCMOS RESET# input. Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTVA16859C supports lowpower standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset to the logic “Low” state, and all input receivers, data (D) and clock (CLK/CLK#).

ICSSSTVA16859C : ICSSSTVA16859C DDR 13-Bit to 26-Bit Registered Buffer Recommended Applications: • DDR Memory Modules: - DDRI (PC1600, PC2100) - DDR333 (PC2700) - DDRI-400 (PC3200) • Provides complete DDR DIMM solution with ICS93V857 or ICS95V857 • SSTL_2 compatible data registers Product Features: • Differential clock signals • Meets SSTL_2 signal data • Supports SSTL_2 class I specifications on outputs • Low-voltage operation - VDD = 2.3V to 2.7V • Available in 64 pin TSSOP and 56 pin MLF packages • Exceeds ICSSSTVN16859 performance Truth Table1 RESET# L H H H Notes: Inputs CLK CLK# X or X or Floating Floating ↑↓ ↑↓ L or H L or H Q Outputs DQ X or Floating L HH LL X Q0(2) 1. H = "High" .




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