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HYB18T256400BFL

Qimonda
Part Number HYB18T256400BFL
Manufacturer Qimonda
Description 256-Mbit Double-Data-Rate-Two SDRAM
Published Apr 15, 2010
Detailed Description July 2007 www.DataSheet4U.com HY[B/I]18T256400B[C/F](L) HY[B/I]18T256800B[C/F](L) HY[B/I]18T256160B[C/F](L) 256-Mbit Do...
Datasheet PDF File HYB18T256400BFL PDF File

HYB18T256400BFL
HYB18T256400BFL

Overview
July 2007 www.
DataSheet4U.
com HY[B/I]18T256400B[C/F](L) HY[B/I]18T256800B[C/F](L) HY[B/I]18T256160B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev.
1.
11 Internet Data Sheet www.
DataSheet4U.
com HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM HY[B/I]18T256400B[C/F](L), HY[B/I]18T256800B[C/F](L), HY[B/I]18T256160B[C/F](L) Revision History: 2007-07, Rev.
1.
11 Page All All Subjects (major changes since last revision) Adapted Internet edition.
Editorial change Added product types with industrial temperature Previous Revision: 2006-12, Rev.
1.
00 Previous Revision: 2007-05, Rev.
1.
10 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to: techdoc@qimonda.
com qag_techdoc_rev400 / 3.
2 QAG / 2006-08-07 11172006-LBIU-F1TN 2 Internet Data Sheet www.
DataSheet4U.
com HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM 1 Overview This chapter gives an overview of the 256-Mbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics.
1.
1 Features The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • Off-Chip-Driver impedance adjustment (OCD) and • 1.
8 V ± 0.
1 V Power Supply 1.
8 V ± 0.
1 V (SSTL_18) compatible I/O On-Die-Termination (ODT) for better signal quality • DRAM organizations with 4, 8 and 16 data in/outputs • Auto-Precharge operation for read and write bursts • Double Data Rate architecture: two data transfers per • Auto-Refresh, Self-Refresh and power saving Powerclock cycle four internal banks for concurrent operation Down modes • Programmable CAS Latency: 3, 4, 5 and 6 • Average Refresh Period 7.
8 μs at a TCASE lower than • Programmable Burst Length: 4 and 8 85 °C, 3.
9 μs between 85 °C and 95 °C • Differentia...


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