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SIS5501

Silicon Integrated System
Part Number SIS5501
Manufacturer Silicon Integrated System
Description (SIS5501 - SIS5503) PCI/ISA Cache Memory Controller
Published Apr 15, 2010
Detailed Description www.DataSheet4U.com Pentium/P54C PCI/ISA Chipset 1 5501/5502/5503 Overview SiS5501 SiS5502 SiS5503 PCI/ISA Cache Memory...
Datasheet PDF File SIS5501 PDF File

SIS5501
SIS5501

Overview
www.
DataSheet4U.
com Pentium/P54C PCI/ISA Chipset 1 5501/5502/5503 Overview SiS5501 SiS5502 SiS5503 PCI/ISA Cache Memory Controller (PCMC) PCI Local Data Buffer (PLDB) PCI System I/O (PSIO) A whole set of the SiS5501, 5502, and 5503 provides fully integrated support for the Pentium/P54C PCI/ISA system.
The chipset is developed by using a very high level of function integration and system partitioning.
With the SiS5501, SiS5502, and SiS5503 chipset, only 12 TTLs (include 3 DRAM address buffer) are required to implement a low cost, high performance, Pentium/P54C PCI/ISA system.
Figure 1 shows the system block diagram.
SRAM CPU Pentium , P54C 373 Address Data HOST BUS PCMC 5501 Address/Data 244 DRAM PLDB 5502 PCI BUS PSIO 5503 IDE Buffers IDE Drives PCI Local Device #1 ISA Device #1 PCI Local Device #2 ISA Device #2 * * * * * * XD BUS 245 Address Data ISA BUS Figure 1.
1 System Block Diagram Preliminary V2.
0 April 2, 1995 1 Silicon Integrated Systems Corporation www.
DataSheet4U.
com SiS5501 PCI/ISA Cache Memory Controller 2.
SiS5501 2.
1 Features • • • • Supports the 510\60, 567\66, 735\90, 815\100 MHz and 75 MHz Pentium Processor Supports M1 and Other Pentium Compatible CPU Supports the Pipelined Address Mode of the Pentium or the P54C Processor Integrated Second Level ( L2 ) Cache Controller - Write Through and Write Back Cache Modes - 8 bits or 7 bits Tag with Direct Mapped Organization - Supports Standard and Burst SRAMs - Supports 64 KBytes to 2 MBytes Cache Sizes - Cache Read/Write Cycle of 3-2-2-2 or 4-2-2-2 Using Standard SRAMs at 66 MHz - Cache Read/Write Cycle of 3-1-1-1 Using Burst SRAMs at 66 MHz • Integrated DRAM Controller - Supports 8 Banks of SIMMs up to 512 MBytes of Cacheable Main Memory - Supports " Table- Free " DRAM Configuration - Concurrent Write Back - CAS#-before-RAS# Transparent DRAM Refresh - Supports 256K/512K/1M/2M/4M/16M xN 70ns Fast Page Mode and EDO DRAM - The Fastest Burst Cycle Speed for FP and EDO are 6-3-3-3 and ...


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