DatasheetsPDF.com

IS61LP6436A

Part Number	IS61LP6436A
Manufacturer	Integrated Silicon Solution
Description	64K x 32- 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM
Published	Apr 24, 2010
Detailed Description	IS61LP6432A IS61LP6436A 64K x 32, 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM FEATURES • Internal self-timed write cycle •...
Datasheet	IS61LP6436A PDF File

Overview

IS61LP6432A IS61LP6436A 64K x 32, 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • JEDEC 100-Pin TQFP package • Power-down snooze mode • Power Supply: +3.
3V VDD +3.
3V or 2.
5V VDDQ (I/O) • Lead-free available www.
DataSheet4U.
com ISSI ® SEPTEMBER 2005 DESCRIPTION The ISSI IS61LP6432A/36A is a high-speed synchronous static RAM designed to provide a burstable, high-performance memory for high speed networking and communication applications.
The IS61LP6432A is organized as 64K words by 32 bits and the IS61LP6436A is organized as 64K words by 36 bits.
Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, highspeed SRAM core, and high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the rising edge of the clock input.
Write cycles can be from one to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW.
A LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins.
Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TI...

Similar Datasheet

IS61LP6432A 64K x 32 or 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM - Integrated Silicon Solution
IS61LP6432A 64K x 32- 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM - Integrated Silicon Solution
IS61LP6436A 64K x 32 or 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM - Integrated Silicon Solution
IS61LP6436A 64K x 32- 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM - Integrated Silicon Solution

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)