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A48P3616

Part Number	A48P3616
Manufacturer	AMIC Technology
Description	8M X 16 Bit DDR DRAM
Published	Apr 28, 2010
Detailed Description	www.DataSheet4U.com A48P3616 Preliminary Document Title 8M X 16 Bit DDR DRAM Revision History Rev. No. 0.0 8M X 16 Bit...
Datasheet	A48P3616 PDF File

Overview

www.
DataSheet4U.
com A48P3616 Preliminary Document Title 8M X 16 Bit DDR DRAM Revision History Rev.
No.
0.
0 8M X 16 Bit DDR DRAM History Initial issue Issue Date September 5, 2005 Remark Preliminary Preliminary (September 2005, Version 0.
0) AMIC Technology, Corp.
www.
DataSheet4U.
com A48P3616 Preliminary Feature CAS Latency and Frequency CAS Latency 2 2.
5 3 Maximum Operating Frequency (MHz) DDR466 DDR400 DDR333 DDR266 (43) (5T) (6K) (75B) 133 100 166 166 133 233 200 • Differential clock inputs (CK and CK ) • Four internal banks for concurrent operation • Data mask (DM) for write data.
• DLL aligns DQ and DQS transitions with CK transitions.
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS.
• Burst lengths: 2, 4, or 8 • CAS Latency: 2 & 2.
5 for 6K/75B, 2.
5 & 3 for 5T, 3 for 43 • Auto Precharge option for each burst access • Auto Refresh and Self Refresh Modes • 15.
6µs Maximum Average Periodic Refresh Interval • 2.
5V (SSTL_2 compatible) I/O • VDD = VDDQ = 2.
5V ± 0.
2V (6K/75B) • VDD = VDDQ = 2.
6V ± 0.
1V (5T/43) • Lead-free and Halogen-free product available 8M X 16 Bit DDR DRAM • Double data rate architecture: two data transfers per clock cycle.
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
• DQS is edge-aligned with data for reads and is centeraligned with data for writes.
General Description The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits.
It is internally configured as a quad-bank DRAM and is based on Nanya’s 110nm process.
The 128Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation.
The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single read or write access for the 128Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle da...

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