Part Number A48P3616
Manufacturer AMIC Technology
Title 8M X 16 Bit DDR DRAM
Description The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRA...
Features CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR466 DDR400 DDR333 DDR266 (43) (5T) (6K) (75B) 133 100 166 166 133 233 200
• Differential clock inputs (CK and CK )
• Four internal banks for concurrent operation
• Data mask (DM) for write data.
• DLL aligns DQ and DQ...

File Size 2.23MB
Datasheet A48P3616 PDF File

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A48P3616B : The 128Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128Mb DDR SDRAM effectively consists of a single 2nbit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller.

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