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IS45S16100C1

Integrated Silicon Solution
Part Number IS45S16100C1
Manufacturer Integrated Silicon Solution
Description 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
Published Apr 30, 2010
Detailed Description IS45S16100C1 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 143 MHz • Full...
Datasheet PDF File IS45S16100C1 PDF File

IS45S16100C1
IS45S16100C1

Overview
IS45S16100C1 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks can be operated simultaneously and independently • Dual internal bank controlled by A11 (bank select) • Single 3.
3V power supply • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • 4096 refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Byte controlled by LDQM and UDQM • Automotive Temperature Range Option A: 0oC to +70oC Option A1: -40oC to +85oC • Packages: 400-mil 50-pin TSOP-II, 60-ball fBGA • Lead-free package option www.
DataSheet4U.
com ISSI JANUARY 2006 ® DESCRIPTION ISSI’s 16Mb Synchronous DRAM IS45S16100C1 is organized as a 524,288-word x 16-bit x 2-bank for improved performance.
The synchronous DRAMs achieve high-speed data transfer using pipeline architecture.
All inputs and outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS 50-Pin TSOP (Type II) VDD DQ0 DQ1 GNDQ DQ2 DQ3 VDDQ DQ4 DQ5 GNDQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 GND DQ15 IDQ14 GNDQ DQ13 DQ12 VDDQ DQ11 DQ10 GNDQ DQ9 DQ8 VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 GND PIN DESCRIPTIONS A0-A11 A0-A10 A11 A0-A7 DQ0 to DQ15 CLK CKE CS RAS Address Input Row Address Input Bank Select Address Column Address Input Data DQ System Clock Input Clock Enable Chip Select Row Address Strobe Command CAS WE LDQM UDQM VDD GND VDDQ GNDQ NC Column Address Strobe Command Write Enable Lower Bye, Input/Output Mask Upper Bye, Input/Output Mask Power Ground Power Supply for DQ Pin Gr...


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