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ICS874003-02

Integrated Device Technology
Part Number ICS874003-02
Manufacturer Integrated Device Technology
Description PCI EXPRESS JITTER ATTENUATOR
Published May 3, 2010
Detailed Description www.DataSheet4U.com PCI EXPRESS™ JITTER ATTENUATOR ICS874003-02 GENERAL DESCRIPTION The ICS874003-02 is a high perfor...
Datasheet PDF File ICS874003-02 PDF File

ICS874003-02
ICS874003-02

Overview
www.
DataSheet4U.
com PCI EXPRESS™ JITTER ATTENUATOR ICS874003-02 GENERAL DESCRIPTION The ICS874003-02 is a high performance DifIC S ferential-to-LVDS Jitter Attenuator designed for HiPerClockS™ use in PCI Express systems.
In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer.
In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board.
The ICS874003-02 has a bandwidth of 400kHz.
The 400kHz provides an intermediate bandwidth that can easily track tr iangular spread profiles, while providing good jitter attenuation.
The ICS874003-02 uses IDT’s 3 rd Generation FemtoClock TM PLL technology to achive the lowest possible phase noise.
The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards.
FEATURES • Three Differential LVDS output pairs • One Differential clock input • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 98MHz - 320MHz • Input frequency range: 98MHz - 128MHz • VCO range: 490MHz - 640MHz • Cycle-to-cycle jitter: 35ps (maximum) • Supports PCI-Express Spread-Spectrum Clocking • The 400kHz bandwidth mode allows the system designer to make jitter attenuation/tracking skew design trade-offs • 3.
3V operating supply • 0°C to 70°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages F_SEL[2:0] FUNCTION TABLE F_SEL2 0 1 0 1 0 1 Inputs F_SEL1 0 0 1 1 0 0 1 1 F_SEL0 0 0 0 0 1 1 1 1 Outputs QA0/nQA0, QA0/nQA0 ÷2 ÷5 ÷4 ÷2 ÷2 ÷5 ÷4 ÷4 QB0/nQB0 ÷2 ÷2 ÷2 ÷4 ÷5 ÷4 ÷5 ÷4 BLOCK DIAGRAM OEA Pullup F_SEL2:0 Pulldown 3 0 1 PIN ASSIGNMENT QA0 ÷5 ÷4 ÷2 (default) CLK Pulldown nCLK Pullup nQA0 QA1 Phase Detector VCO 490 - 640MHz 3 nQA1 QA1 VDDO QA0 nQA0 MR F_S...


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