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HYB18H512321BF-10

Qimonda AG
Part Number HYB18H512321BF-10
Manufacturer Qimonda AG
Description 512-Mbit GDDR3 Graphics RAM
Published May 3, 2010
Detailed Description September 2007 www.DataSheet4U.com HYB18H512321BF–11/12/14 HYB18H512321BF–08/10 512-Mbit GDDR3 Graphics RAM GDDR3 Grap...
Datasheet PDF File HYB18H512321BF-10 PDF File

HYB18H512321BF-10
HYB18H512321BF-10

Overview
September 2007 www.
DataSheet4U.
com HYB18H512321BF–11/12/14 HYB18H512321BF–08/10 512-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM RoHS compliant Internet Data Sheet Rev.
1.
1 Internet Data Sheet www.
DataSheet4U.
com HYB18H512321BF 512-Mbit GDDR3 HYB18H512321BF–11/12/14 HYB18H512321BF–08/10 Revision History: 2007-09, Rev.
1.
1 Page 34 34 Subjects (major changes since last revision) Table 41 max.
CL changed from 16 to 13 Table 41 - Timing Parameters for -8 updated Previous Revision: Rev.
1.
0, 2007-05 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to: techdoc@qimonda.
com qag_techdoc_rev411 / 3.
31 QAG / 2007-01-22 05292007-WAU2-UU95 2 Internet Data Sheet www.
DataSheet4U.
com HYB18H512321BF 512-Mbit GDDR3 1 1.
1 • • • • • • • • • • • • • • Overview Features • Data mask for write commands • Single ended READ strobe (RDQS) per byte.
RDQS edgealigned with READ data • Single ended WRITE strobe (WDQS) per byte.
WDQS center-aligned with WRITE data • DLL aligns RDQS and DQ transitions with Clock • Programmable IO interface including on chip termination (ODT) • Autoprecharge option with concurrent auto precharge support • 8k Refresh (32ms) • Autorefresh and Self Refresh • PG–TFBGA–136 package (10mm × 14mm) • Calibrated output drive.
Active termination support • RoHS Compliant Product1) This chapter lists all main features of the product family HYB18H512321BF and the ordering information.
2.
0 V VDDQ IO voltage HYB18H512321BF–08/10 2.
0 V VDD core voltage HYB18H512321BF–08/10 1.
8 V VDDQ IO voltage HYB18H512321BF–11/12/14 1.
8 V VDD core voltage HYB18H512321BF–11/12/14 Organization: 2048K × 32 × 8 banks 4096 rows and 512 columns (128 burst start locations) per bank Differential clock inputs (CLK and CLK) CAS latencies of 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 Wri...


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