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UL62H256A

Zentrum Mikroelektronik Dresden AG
Part Number UL62H256A
Manufacturer Zentrum Mikroelektronik Dresden AG
Description Low Voltage Automotive Fast 32K x 8 SRAM
Published May 14, 2010
Detailed Description UL62H256A Low Voltage Automotive Fast 32K x 8 SRAM Features ! 32768 x 8 bit static CMOS RAM ! 35 and 55 ns Access Time !...
Datasheet PDF File UL62H256A PDF File

UL62H256A
UL62H256A

Overview
UL62H256A Low Voltage Automotive Fast 32K x 8 SRAM Features ! 32768 x 8 bit static CMOS RAM ! 35 and 55 ns Access Time ! Common data inputs and Description go High-Z until the new information is available.
The data outputs have no preferred state.
The Read cycle is finished by the falling edge of W, or by the rising edge of E, respectively.
Data retention is guaranteed down to 2 V.
With the exception of E, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required.
The UL62H256A is a static RAM manufactured using a CMOS process technology with the following operating modes: data outputs - Read - Standby ! Three-state outputs - Write - Data Retention ! Typ.
operating supply current The memory array is based on a 35 ns: 45 mA 6-Transistor cell.
55 ns: 30 mA ! Standby current < 40 µA at 125 °C The circuit is activated by the falling edge of E.
The address and ! TTL/CMOS-compatible control inputs open simultaneously.
! Power supply voltage 2.
5 - 3.
6 V According to the information of W ! Operating temperature range www.
DataSheet4U.
com -40 °C to 85 °C and G, the data inputs, or outputs, -40 °C to 125 °C are active.
In a Read cycle, the data outputs are activated by the ! QS 9000 Quality Standard falling edge of G, afterwards the ! ESD protection > 2000 V (MIL STD 883C M3015.
7) data word will be available at the outputs DQ0-DQ7.
After the ! Latch-up immunity >100 mA address change, the data outputs ! Package: SOP28 (300/330 mil) Pin Configuration Pin Description A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 Signal Name A0 - A14 DQ0 - DQ7 E G W VCC VSS Signal Description Address Inputs Data In/Out Chip Enable Output Enable Write Enable Power Supply Voltage Ground SOP 21 20 19 18 17 16 15 Top View May 07, 2004 1 UL62H256A Block Diagram A6 A7 A8 A9 A10 A11 A12 A13 A14 Row Address Inputs Row Decoder Memory Cell Array 512 Rows x 64...


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