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TV00570002CDGB

Part Number	TV00570002CDGB
Manufacturer	Toshiba
Description	MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS
Published	May 14, 2010
Detailed Description	TV00570002/003CDGB TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS TENTATIVE Pseudo SRAM and NOR Flash Memory ...
Datasheet	TV00570002CDGB PDF File

Overview

TV00570002/003CDGB TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS TENTATIVE Pseudo SRAM and NOR Flash Memory Mixed Multi-Chip Package DESCRIPTION The TV00570002/003CDGB is a mixed multi-chip package containing a 33,554,432-bit pseudo static RAM and a 134,217,728-bit Nor Flash Memory.
The TV00570002/003CDGB is available in a 81-pin BGA package making it suitable for a variety of applications.
MCP Features • • • Power supply voltage of 2.
7 to 3.
3 V Operating temperature of −30° to 85°C Package P-TFBGA81-0710-0.
80BZ (Weight: 0.
15 g) Nor Flash Memory Features • • Organization: 8M × 16 bits Power dissipation Read operating : 55 mA maximum Address Increment Read operation: 24mA maximum Page Read operating : 5 mA maximum Program / Erase operating: 15 mA maximum Standby : 10 μA maximum Access time : Random : 70 ns @CL=30pF Page : 25 ns @CL=30pF Functions Simultaneous Read/Write Page read Auto-Program , Auto Page Program Auto Block Erase , Auto Chip Erase Program Suspend / Resume Erase Suspend/Resume Data polling / Toggle bit Password block protection Block Protection/Boot Block Protection Automatic Sleep, supports for hidden ROM Area Common Flash Memory Interface (CFI) Block erase architecture 8 × 8 Kbytes / 127 × 64 Kbytes Bank architecture 16 Mbits × 8 Banks Boot block architecture TV00570002CDGB : top boot block TV00570003CDGB : bottom boot block Mode control Compatible with JEDEC standard commands Erase/Program cycles 100,000 cycles typ.
Pseudo SRAM Features www.
DataSheet4U.
com • Power dissipation • Organization : 2M × 16 bits Operating : 40 mA maximum Standby : 150 μA maximum Deep power-down standby : 5 μA maximum Access time : Random / Page : 70 ns / 30 ns @CL=30pF Page read operation by 8 words Deep power-down mode : Memory cell data invalid • • • • • • • • • • 2008-05-08 1/9 TV00570002/003CDGB PIN ASSIGNMENT (TOP VIEW) 1 2 3 4 5 6 7 8 A B C D E F G H J K NC NC NC A3 A2 A1 A0 CEf CE1ps NC NC A7 A6 A5 A4 VSS OE NC LB UB NC WP/ACC NC WE NC ...

Similar Datasheet

TV00570002CDGB MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS - Toshiba

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