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MC74HC365A

ON Semiconductor
Part Number MC74HC365A
Manufacturer ON Semiconductor
Description Hex 3-State Noninverting Buffer
Published Aug 15, 2010
Detailed Description MC74HC365A Hex 3-State Noninverting Buffer with Common Enables High−Performance Silicon−Gate CMOS The MC74HC365A is ide...
Datasheet PDF File MC74HC365A PDF File

MC74HC365A
MC74HC365A

Overview
MC74HC365A Hex 3-State Noninverting Buffer with Common Enables High−Performance Silicon−Gate CMOS The MC74HC365A is identical in pinout to the LS365.
The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device is a high−speed hex buffer with 3−state outputs and two common active−low Output Enables.
When either of the enables is high, the buffer outputs are placed into high−impedance states.
The HC365A has noninverting outputs.
Features • Output Drive Capability: 15 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.
0 to 6.
0 V • Low Input Current: 1.
0 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirements Defined by JEDEC Standard No.
7A • Chip Complexity: 90 FETs or 22.
5 Equivalent Gates • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.
onsemi.
com 16 1 MARKING DIAGRAMS 16 SOIC−16 D SUFFIX CASE 751B HC365AG AWLYWW 1 16 16 1 TSSOP−16 DT SUFFIX CASE 948F HC 365A ALYWG G 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2009 1 August, 2019 − Rev.
3 Publication Order Number: MC74HC365A/D MC74HC365A OUTPUT ENABLE 1 1 A0 2 Y0 3 A1 4 Y1 5 A2 6 Y2 7 GND 8 16 VCC 15 OUTPUT ENABLE 2 14 A5 13 Y5 12 A4 11 Y4 10 A3 9 Y3 Figure 1.
Pin Assignment FUNCTION TABLE Inputs Output Enable Enable 1 2 A Y L L L L L L H H H X X Z X H X Z X = don’t care Z = high impedance A0 2 A1 4 A2 6 3 Y0 5 Y1 7 Y2 A3 10 A4 12 A5 14 9 Y3 11 Y4 13 Y5 O...


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