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CY7C1911CV18

Part Number	CY7C1911CV18
Manufacturer	Cypress Semiconductor
Description	(CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
Published	Dec 9, 2010
Detailed Description	CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features ■ Config...
Datasheet	CY7C1911CV18 PDF File

Overview

CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features ■ Configurations CY7C1311CV18 – 2M x 8 CY7C1911CV18 – 2M x 9 CY7C1313CV18 – 1M x 18 CY7C1315CV18 – 512K x 36 Separate independent read and write data ports ❐ Supports concurrent transactions 300 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches Echo clocks (CQ and CQ) simplify data capture in high-speed systems Single multiplexed address input bus latches address inputs for both read and write ports Separate port selects for depth expansion Synchronous internally self-timed writes QDR™-II operates with 1.
5 cycle read latency when the Delay Lock Loop (DLL) is enabled Operates a...

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CY7C1911CV18 (CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture - Cypress Semiconductor

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