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CY7C1482BV33

Part Number	CY7C1482BV33
Manufacturer	Cypress Semiconductor
Description	(CY7C148xBV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
Published	Dec 9, 2010
Detailed Description	CY7C1480BV33 CY7C1482BV33, CY7C1486BV33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ ■ ■ ■ ■ ■ Fun...
Datasheet	CY7C1482BV33 PDF File

Overview

CY7C1480BV33 CY7C1482BV33, CY7C1486BV33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ ■ ■ ■ ■ ■ Functional Description The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation.
All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).
The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at the rising edge of the clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active.
Subsequent burst addresses may be internally generated as controlled by the Advance...

Similar Datasheet

CY7C1482BV25 (CY7C148xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM - Cypress Semiconductor
CY7C1482BV33 (CY7C148xBV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM - Cypress Semiconductor

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