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HY5S7B6ALFP-H

Hynix Semiconductor
Part Number HY5S7B6ALFP-H
Manufacturer Hynix Semiconductor
Description 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O
Published Mar 2, 2011
Detailed Description 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O Document Title 4Bank x 8M x 16bits Synchronous DRAM Revision Histo...
Datasheet PDF File HY5S7B6ALFP-H PDF File

HY5S7B6ALFP-H
HY5S7B6ALFP-H

Overview
512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O Document Title 4Bank x 8M x 16bits Synchronous DRAM Revision History Revision No.
0.
1 0.
2 1.
0 1.
1 Initial Draft Inserted 166MHz Product Release Insert (Page10) DPD specification [IDD7 : 10uA min] History Draft Date Aug.
2006 Sep.
2006 May.
2007 July.
2007 Remark Preliminary Preliminary This document is a general product description and is subject to change without notice.
Hynix does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Rev 1.
1 / July.
2007 1 512Mbit (32Mx16bit) Mobile SDR Memory HY5S7B6ALF(P) Series DESCRIPTION The Hynix HY5S7B6ALF(P) is suited for non-PC application which use the batteries such as PDAs, 2.
5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.
The Hynix 512M Mobile SDRAM is 536,870,912-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the main memory applications which requires large memory density and high bandwidth.
It is organized as 4banks of 8,388,608x16.
Mobile SDRAM is a type of DRAM which operates in synchronization with input clock.
The Hynix Mobile SDRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK).
The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16 Input/ Output bus.
All the commands are latched in synchronization with the rising edge of CLK.
The Mobile SDRAMs provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8 locations or full page.
An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.
The Mobile SDRAM uses an internal pipelined architecture to achieve high-speed operation.
This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every cl...


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