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PE43073

Peregrine Semiconductor
Part Number PE43073
Manufacturer Peregrine Semiconductor
Description RF Digital Attenuator
Published Apr 6, 2011
Detailed Description Product Specification PE43703 Product Description The PE43703 is a HaRP™-enhanced, high linearity, 7-bit RF Digital Ste...
Datasheet PDF File PE43073 PDF File

PE43073
PE43073

Overview
Product Specification PE43703 Product Description The PE43703 is a HaRP™-enhanced, high linearity, 7-bit RF Digital Step Attenuator (DSA).
This highly versatile DSA covers a 31.
75 dB attenuation range in 0.
25 dB, 0.
5 dB, or 1.
0 dB steps.
The customer can choose which step size and associated specifications are best suited for their application.
The Peregrine 50Ω RF DSA provides multiple CMOS control interfaces and an optional external Vss feature.
It maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and low power consumption.
Performance does not change with Vdd due to on-board regulator.
This next generation Peregrine DSA is available in a 5x5 mm 32-lead QFN footprint.
The PE43703 is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS.
Figure 1.
Package Type 32-lead 5x5x0.
85 mm QFN Package 50 Ω RF Digital Attenuator 7-bit, 31.
75 dB, DC-6.
0 GHz, VssEXT option Features • HaRP™-enhanced UltraCMOS™ device • Attenuation options: 0.
25 dB, 0.
5 dB, or 1.
0 dB steps to 31.
75 dB • 0.
25 dB monotonicity for ≤ 4.
0 GHz • 0.
5 dB monotonicity for ≤ 5.
0 GHz • 1 dB monotonicity for ≤ 6.
0 GHz • High Linearity: Typical +59 dBm IIP3 • Excellent low-frequency performance • Optional External Vss Control (VssEXT) • 3.
3 V or 5.
0 V Power Supply Voltage • Fast switch settling time • Programming Modes: Direct Parallel Latched Parallel • Serial-Addressable: Program up to eight addresses 000 - 111 • High-attenuation state @ power-up (PUP) • • • CMOS Compatible • No DC blocking capacitors required Figure 2.
Functional Schematic Diagram Switched Attenuator Array RF Input RF Output Parallel Control 7 Serial In www.
DataSheet4U.
com CLK LE Control Logic Interface A0 A1 A2 P/S (optional) VssEXT ©2008-2009 Peregrine Semiconductor Corp.
All rights reserved.
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