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CY7C1163KV18

Part Number	CY7C1163KV18
Manufacturer	Cypress Semiconductor
Description	18-Mbit QDR II SRAM Four-Word Burst Architecture
Published	Apr 15, 2011
Detailed Description	CY7C1161KV18, CY7C1176KV18 CY7C1163KV18, CY7C1165KV18 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Rea...
Datasheet	CY7C1163KV18 PDF File

Overview

CY7C1161KV18, CY7C1176KV18 CY7C1163KV18, CY7C1165KV18 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.
5 Cycle Read Latency) Features ■ Configurations With Read Cycle Latency of 2.
5 cycles: CY7C1161KV18 – 2 M x 8 CY7C1176KV18 – 2 M x 9 CY7C1163KV18 – 1 M x 18 CY7C1165KV18 – 512 K x 36 Separate independent read and write data ports ❐ Supports concurrent transactions 550-MHz clock for high bandwidth Four-word burst for reducing address bus frequency Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz Available in 2.
5 clock cycle latency Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only Echo clocks (CQ an...

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CY7C1163KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture - Cypress Semiconductor

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