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CY7C1424JV18

Part Number	CY7C1424JV18
Manufacturer	Cypress Semiconductor
Description	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
Published	Apr 15, 2011
Detailed Description	CY7C1422JV18, CY7C1429JV18 CY7C1423JV18, CY7C1424JV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features ■ ■ ■ ...
Datasheet	CY7C1424JV18 PDF File

Overview

CY7C1422JV18, CY7C1429JV18 CY7C1423JV18, CY7C1424JV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ Functional Description The CY7C1422JV18, CY7C1429JV18, CY7C1423JV18, and CY7C1424JV18 are 1.
8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate I/O (DDR-II SIO) architecture.
The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array.
The read port has data outputs to support read operations and the write port has data inputs to support write operations.
The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices.
Access to each port is accomplished through a common address bus.
Addresses for read and write are latched on alternate rising edges of the input (K) clock.
Write data is registered on the rising edges of both K and K.
Read data is driven on the rising edges of C and C if provided, or on the ris...

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CY7C1424JV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture - Cypress Semiconductor

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