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CY7C1916JV18

Part Number	CY7C1916JV18
Manufacturer	Cypress Semiconductor
Description	18-Mbit DDR-II SRAM 2-Word Burst Architecture
Published	Apr 15, 2011
Detailed Description	CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ ...
Datasheet	CY7C1916JV18 PDF File

Overview

CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ Functional Description The CY7C1316JV18, CY7C1916JV18, CY7C1318JV18, and CY7C1320JV18 are 1.
8V Synchronous Pipelined SRAMs equipped with DDR-II architecture.
The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter.
Addresses for read and write are latched on alternate rising edges of the input (K) clock.
Write data is registered on the rising edges of both K and K.
Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided.
Each address location is associated with two 8-bit words in the case of CY7C1316JV18 and two 9-bit words in the case of CY7C1916JV18 that burst sequentially into or out of the device.
The burst counter always starts with a ‘0’ internally in the case of CY7C1316JV18 and CY7C1916JV18.
For CY7C1318JV18 and CY7C1320JV18, the burst count...

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CY7C1916JV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture - Cypress Semiconductor

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