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CY7C1320KV18

Part Number	CY7C1320KV18
Manufacturer	Cypress Semiconductor
Description	18-Mbit DDR II SRAM Two-Word Burst Architecture
Published	Apr 15, 2011
Detailed Description	 CY7C1316KV18, CY7C1916KV18 CY7C1318KV18, CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture 18-Mbit DDR II...
Datasheet	CY7C1320KV18 PDF File

Overview

 CY7C1316KV18, CY7C1916KV18 CY7C1318KV18, CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture 18-Mbit DDR II SRAM Two-Word Burst Architecture Features ■ ■ ■ ■ ■ Configurations CY7C1316KV18 – 2 M × 8 CY7C1916KV18 – 2 M × 9 CY7C1318KV18 – 1 M × 18 CY7C1320KV18 – 512 K × 36 18-Mbit density (2 M × 8, 2 M × 9, 1 M × 18, 512 K × 36) 333-MHz clock for high bandwidth Two-word burst for reducing address bus frequency Double data rate (DDR) interfaces  (data transferred at 666 MHz) at 333 MHz Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches Echo clocks (CQ and CQ) simplify data capture in high-speed systems Synchronous internally self-timed writes DDR II operates with 1.
5 cycle read latency when DOFF is asserted HIGH Operates similar to DDR-I device with 1 cycle read latency when DOFF is asserted LOW 1.
8 V core power supply with HSTL inputs and outputs Variable drive HSTL output buffers Expanded HSTL output voltage (1.
4 V–VDD) ❐ Supports both 1.
5 V and 1.
8 V I/O supply Available in 165-ball FBGA package (13 × 15 × 1.
4 mm) Offered in both Pb-free and non Pb-free packages JTAG 1149.
1 compatible test access port Phase locked loop (PLL) for accurate data placement Functional Description The CY7C1316KV18, CY7C1916KV18, CY7C1318KV18, and CY7C1320KV18 are 1.
8 V synchronous pipelined SRAM equipped with DDR II architecture.
The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.
Addresses for read and write are latched on alternate rising edges of the input (K) clock.
Write data is registered on the rising edges of both K and K.
Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided.
Each address location is associated with two 8-bit words in the case of CY7C1316KV18 and two 9-bit words in the case of CY7C1916KV18 that burst seq...

Similar Datasheet

CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture - Cypress Semiconductor

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