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L29C525JC15

Part Number	L29C525JC15
Manufacturer	LOGIC Devices Incorporated
Description	Dual Pipeline Register
Published	Mar 22, 2005
Detailed Description	L29C525 DEVICES INCORPORATED Dual Pipeline Register L29C525 DEVICES INCORPORATED Dual Pipeline Register DESCRIPTION ...
Datasheet	L29C525JC15 PDF File

Overview

L29C525 DEVICES INCORPORATED Dual Pipeline Register L29C525 DEVICES INCORPORATED Dual Pipeline Register DESCRIPTION The L29C525 is a high-speed, low power CMOS pipeline register.
It is pin-for-pin compatible with the AMD Am29525.
The L29C525 can be configured as two independent 8-level pipelines or as a single 16-level pipeline.
The configuration implemented is determined by the instruction code (I1-0) as shown in Table 2.
The I1-0 instruction code controls the internal routing of data and loading of each register.
For instruction I1-0 = 00 (Push A and B), data applied at the D 7-0 inputs is latched into register A0 on the rising edge of CLK.
The contents of A0 simultaneously move to register A1, A1 moves to A2, and so on.
The contents of register A7 are wrapped back to register B0.
The registers on the B side are similarly shifted, with the contents of register B7 lost.
Instruction I1-0 = 01 (Push B) acts similarly to the Push A and B instruction, except that only the B side registers are shifted.
The input data is applied to register B0, and the contents of register B7 are lost.
The contents of the A side registers are unaffected.
Instruction I1-0 = 10 (Push A) is identical to the Push B instruction, except that the A side registers are shifted and the B side registers are unaffected.
Instruction I1-0 = 11 (Hold) causes no internal data movement.
It is equivalent to preventing the application of a clock edge to any internal register.
The contents of any of the registers is selectable at the output through the use of the S3-0 control inputs.
The independence of the I and S control lines allows simultaneous reading and writing.
Encoding for the S3-0 controls is given in Table 3.
FEATURES u u u u u u u u Dual 8-Deep Pipeline Register Configurable to Single 16-Deep Low Power CMOS Technology Replaces AMD Am29525 Load, Shift, and Hold Instructions Separate Data In and Data Out Pins Three-State Outputs Package Styles Available: • 28-pin Plastic DIP • 28-pin Plastic ...

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