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CY8C20224

Cypress Semiconductor
Part Number CY8C20224
Manufacturer Cypress Semiconductor
Description Programmable System-on-Chip
Published May 2, 2011
Detailed Description CapSense PSoC Programmable System-on-Chip™ CapSense® PSoC® Programmable System-on-Chip CY8C20224, CY8C20324 CY8C20424, ...
Datasheet PDF File CY8C20224 PDF File

CY8C20224
CY8C20224

Overview
CapSense PSoC Programmable System-on-Chip™ CapSense® PSoC® Programmable System-on-Chip CY8C20224, CY8C20324 CY8C20424, CY8C20524 ® ® Features ■ ■ Low power, configurable CapSense® ❐ Configurable capacitive sensing elements ❐ operating voltage ❐ Operating voltage: 2.
4 V to 5.
25 V ❐ Low operating current • Active 1.
5 mA (at 3.
0 V, 12 MHz) • Sleep 2.
8 µA (at 3.
3 V) ❐ Supports up to 25 capacitive buttons ❐ Supports one slider ❐ Up to 10 cm proximity sensing ❐ Supports up to 28 general-purpose I/O (GPIO) pins • Drive LEDs and other outputs ❐ Configurable LED behavior (fading, strobing) ❐ LED color mixing (RBG LEDs) ❐ Pull-up, high Z, open-drain, and CMOS drive modes on all GPIOs ❐ Internal ±5.
0% 6 or12 MHz main oscillator ❐ Internal low-speed oscillator at 32 kHz ❐ Low external component count • No external crystal or oscillator components • No external voltage regulator required High-performance CapSense ❐ Ultra fast scan speed —1 kHz (nominal) ❐ Reliable finger detection through 5 mm thick acrylic ❐ Excellent EMI and AC noise immunity Industry best flexibility ❐ 8 KB flash program storage 50,000 erase and write cycles ❐ 512-bytes SRAM data storage ❐ Bootloader for ease of field reprogramming ❐ Partial flash updates ❐ Flexible flash protection modes ❐ Interrupt controller ❐ In-system serial programming (ISSP) ❐ Free complete development tool (PSoC Designer™) ❐ Full-featured, in-circuit emulator and programmer • Full-speed emulation • Complex breakpoint structure • 128 KB trace memory Additional system resources ❐ Configurable communication speeds 2 ❐ I C slave ❐ SPI master and SPI slave ❐ Watchdog and sleep timers ❐ Internal voltage reference ❐ Integrated supervisory circuit ■ ■ Logic Block Diagram Port 3 Port 2 Port 1 Port 0 3V LDO PSoC CORE System Bus Global Analog Interconnect SRAM 512 Bytes Interrupt Controller SROM Flash 8K Sleep and Watchdog CPU Core (M8C) 6/12 MHz Internal Main Oscillator ANALOG SYSTEM CapSense Basic Block Analog Ref.
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