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RX62N

Renesas Technology
Part Number RX62N
Manufacturer Renesas Technology
Description (RX62N / RX621) 100 MHz 32-bit RX MCU
Published Jul 26, 2011
Detailed Description Features Datasheet RX62N/RX621 Group RENESAS 32-Bit MCU R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 100 MHz 32-bit RX MCU wi...
Datasheet PDF File RX62N PDF File

RX62N
RX62N


Overview
Features Datasheet RX62N/RX621 Group RENESAS 32-Bit MCU R01DS0052EJ0110 Rev.
1.
10 Feb 10, 2011 100 MHz 32-bit RX MCU with FPU, 165 DMIPS, up to 512-Kbyte Flash, Ethernet, USB 2.
0 Full-Speed Host/Function/OTG, CAN, 12-bit ADC, TFT-LCD, RTC, up to 14 communication channels Features ■32-bit RX CPU Core  Delivers 165 DMIPS at a maximum operating frequency of 100 MHz  Single Precision 32-bit IEEE-754 Floating Point  Accumulator: 32 × 32 to 64-bit result, one instruction  Mult/Divide Unit, 32 × 32 Multiply in one CPU clock for multiple instructions  Interrupt response in as few as 5 CPU clock cycles  CISC-Harvard Architecture with 5-stage pipeline  Variable length instructions, ultra compact code  Supports the Memory Protection Unit (MPU)  Background JTAG debug plus high-speed trace TFLGA85 7×7mm, 0.
65mm pitch TFLGA145 9×9mm, 0.
65mm pitch LFBGA176 13×13mm, 0.
8mm pitch LQFP100 14×14mm, 0.
5mm pitch LQFP144 20×20mm, 0.
5mm pitch ■Up to 14 Communication Interfaces  (2) USB 2.
0 Full-Speed interfaces with PHY  Supports Host/Function/OTG 10 endpoints for types: Control, Interrupt, Bulk, Isochronous  (1) Ethernet MAC 10/100 Mbps, Half or Full Duplex Supported.
Dedicated DMA with 2-Kbyte transmit and receive FIFOs.
RMII or MII interface to external PHY  (1) CAN ISO11898-1, supports 32 mailboxes  (6) SCI channels: Asynchronous, clock sync, smartcard, and 9-bit modes  (2) I2C interfaces up to 1M bps, SMBus support  (2) RSPI ■Low Power Design and Architecture     2.
7V to 3.
6V operation from a single supply 480 µA/MHz Run Mode with all peripherals on Deep Software Standby Mode with RTC Four low power modes ■Main Flash Memory, no Wait-State      100 MHz operation, 10 nsec read cycle No wait states for read at full CPU speed 256K, 384K, 512K Byte size options For Instructions or Operands Programming from USB, SCI, JTAG, user code ■Data Flash Memory  Up to 32K Bytes with 30K Erase Cycles  Background Erase/Program does not stall CPU ■External Address Spac...


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