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CY25562

Cypress Semiconductor
Part Number CY25562
Manufacturer Cypress Semiconductor
Description Spread Spectrum Clock Generator
Published Aug 8, 2011
Detailed Description CY25562 Spread Spectrum Clock Generator Features ■ ■ ■ ■ Applications ■ ■ ■ 50 to 200 MHz Operating Frequency Range W...
Datasheet PDF File CY25562 PDF File

CY25562
CY25562

Overview
CY25562 Spread Spectrum Clock Generator Features ■ ■ ■ ■ Applications ■ ■ ■ 50 to 200 MHz Operating Frequency Range Wide range of spread selections: 9 Accepts Clock and Crystal Inputs Low Power Dissipation ❐ 70 mW Typ (Fin = 65 MHz) Frequency Spread Disable Function Center Spread Modulation Low Cycle-to-cycle Jitter 8-pin SOIC Package High resolution VGA controllers LCD panels and monitors Workstations and servers Benefits ■ ■ ■ ■ ■ ■ ■ Peak EMI reduction by 8 to 16 dB Fast time to market Cost reduction Logic Block Diagram 300K Xin/ CLK 1 REFERENCE DIVIDER PD CP Loop Filter Xout 8 MODULATION CONTROL FEEDBACK DIVIDER vco VDD 2 INPUT DECODER LOGIC VDD VDD DIVIDER & MUX 4 SSCLK VSS 3 20 K 20 K 20 K VSS 20 K VSS 5 SSCC 6 S1 7 S0 www.
DataSheet4U.
net Cypress Semiconductor Corporation Document Number: 38-07392 Rev.
*C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 15, 2008 [+] Feedback CY25562 Pinout Figure 1.
Pin Configuration XIN/CLK 1 VDD 2 8 XOUT 7 S0 CY25562 VSS 3 SSCLK 4 6 S1 5 SSCC Pin Description Pin # 1 2 3 4 5 6 Pin Name Xin/CLK VDD GND SSCLK SSCC S1 Type I P P O I I Positive power supply Power supply ground SSCG modulated clock output Spread spectrum clock control (enable/disable) function.
SSCG function is enabled when input is high and disabled when input is low.
This pin is pulled high internally.
Tri-level logic input control pin used to select frequency and bandwidth.
Frequency/bandwidth selection and tri-level logic programming.
See Figure 2.
Pin 6 has internal resistor divider network to VDD and VSS.
Refer to Logic Block Diagram on page 1.
Tri-level logic input control pin used to select frequency and bandwidth.
Frequency/Bandwidth selection and tri-level logic programming.
See Figure 2.
Pin 7 has internal resistor divider network to VDD and VSS.
Refer to Logic Block Diagram on page 1.
Oscillator output pin connected to crystal.
Leave this pin unconnected If an external clock driv...


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