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V58C2256404SC

Part Number	V58C2256404SC
Manufacturer	ProMOS Technologies
Description	256 Mbit DDR SDRAM
Published	Oct 21, 2011
Detailed Description	www.DataSheet.co.kr V58C2256(804/404/164)SC*I 256 Mbit DDR SDRAM, INDUSTRIAL TEMPERATURE 4 BANKS X 8Mbit X 8 (804) 4 BA...
Datasheet	V58C2256404SC PDF File

Overview

www.
DataSheet.
co.
kr V58C2256(804/404/164)SC*I 256 Mbit DDR SDRAM, INDUSTRIAL TEMPERATURE 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) 4 BANKS X 16Mbit X 4 (404) 5B DDR400 Clock Cycle Time (tCK2) Clock Cycle Time (tCK2.
5) Clock Cycle Time (tCK3) System Frequency (fCK max) 7.
5 ns 5ns 5ns 200 MHz 5 DDR400 7.
5 ns 6ns 5ns 200 MHz 6 DDR333 7.
5 ns 6 ns 6 ns 166 MHz 7 DDR266 7.
5ns 7ns 7 ns 143 MHz Features ■ High speed data transfer rates with system frequency up to 200 MHz ■ Data Mask for Write Control ■ Four Banks controlled by BA0 & BA1 ■ Programmable CAS Latency: 2, 2.
5, 3 ■ Programmable Wrap Sequence: Sequential or Interleave ■ Programmable Burst Length: 2, 4, 8 for Sequential Type 2, 4, 8 for Interleave Type ■ Automatic and Controlled Precharge Command ■ Power Down Mode ■ Auto Refresh and Self Refresh ■ Refresh Interval: 8192 cycles/64 ms ■ Available in 66-pin 400 mil TSOP or 60 Ball FBGA ■ SSTL-2 Compatible I/Os ■ Double Data Rate (DDR) ■ Bidirectional Data Strobe (DQS) for input and output data, active on both edges ■ On-Chip DLL aligns DQ and DQs transitions with CK transitions ■ Differential clock inputs CK and CK ■ Power Supply 2.
5V ± 0.
2V ■ Power Supply 2.
6V ± 0.
1V for DDR400 ■ tRAS lockout supported ■ Concurrent auto precharge option is supported ■ Industrial Temperature (TA): -40C to +85C *Note: (-5B) Supports PC3200 module with 2.
5-3-3 timing (-5) Supports PC3200 module with 3-3-3 timing (-6) Supports PC2700 module with 2.
5-3-3 timing (-7) Supports PC2100 module with 2-2-2 timing Description The V58C2256(804/404/164)SC*I is a four bank DDR DRAM organized as 4 banks x 8Mbit x 8 (804), 4 banks x 4Mbit x 16 (164), or 4 banks x 16Mbit x 4 (404).
The V58C2256(804/404/164)SC*I achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock.
I/O tra...

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