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GS8170LW36AC-300

GSI Technology
Part Number GS8170LW36AC-300
Manufacturer GSI Technology
Description (GS8170LW36AC / GS8170LW72AC) Late Write SigmaRAM
Published Apr 20, 2012
Detailed Description GS8170LW36/72AC-350/333/300/250 209-Bump BGA Commercial Temp Industrial Temp Features • Late Write mode, Pipelined Read ...
Datasheet PDF File GS8170LW36AC-300 PDF File

GS8170LW36AC-300
GS8170LW36AC-300

Overview
GS8170LW36/72AC-350/333/300/250 209-Bump BGA Commercial Temp Industrial Temp Features • Late Write mode, Pipelined Read mode • JEDEC-standard SigmaRAM™ pinout and package • 1.
8 V +150/–100 mV core power supply • 1.
8 V CMOS Interface • ZQ controlled user-selectable output drive strength • Dual Cycle Deselect • Burst Read and Write option • Fully coherent read and write pipelines • Echo Clock outputs track data output drivers • Byte write operation (9-bit bytes) • 2 user-programmable chip enable inputs • IEEE 1149.
1 JTAG-compliant Serial Boundary Scan • 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package • Pin-compatible with future 36Mb, 72Mb, and 144Mb devices • Pb-Free 209-bump BGA package available 18Mb Σ1x1Lp CMOS I/O Late Write SigmaRAM™ 250 MHz–350 MHz 1.
8 V VDD 1.
8 V I/O Bottom View 209-Bump, 14 mm x 22 mm BGA 1 mm Bump Pitch, 11 x 19 Bump Array www.
DataSheet.
co.
kr SigmaRAM Family Overview GS8170LW36/72A SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs.
This family of wide, very low voltage CMOS I/O SRAMs is designed to operate at the speeds needed to implement economical high performance networking systems.
Functional Description Because SigmaRAMs are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock.
Write cycles are internally self-timed and initiated by the rising edge of the clock input.
This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.
ΣRAMs support pipelined reads utilizing a rising-edgetriggered output register.
They also utilize a Dual Cycle Deselect (DCD) output deselect protocol.
ΣRAMs are offered in a number of configurations including Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by these RAMs mainly involve various approaches to write cueing and...


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