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AD5684R

Analog Devices
Part Number AD5684R
Manufacturer Analog Devices
Description Quad 16-/14-/12-Bit nanoDAC
Published Aug 6, 2012
Detailed Description Data Sheet Quad, 16-/14-/12-Bit nanoDAC+ with 2 ppm/°C Reference, SPI Interface AD5686R/AD5685R/AD5684R INTERFACE LOGI...
Datasheet PDF File AD5684R PDF File

AD5684R
AD5684R

Overview
Data Sheet Quad, 16-/14-/12-Bit nanoDAC+ with 2 ppm/°C Reference, SPI Interface AD5686R/AD5685R/AD5684R INTERFACE LOGIC 10485-001 FEATURES High relative accuracy (INL): ±2 LSB maximum at 16 bits Low drift 2.
5 V reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.
1% of FSR maximum Offset error: ±1.
5 mV maximum Gain error: ±0.
1% of FSR maximum High drive capability: 20 mA, 0.
5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.
8 V logic compatibility 50 MHz SPI with readback or daisy chain Low glitch: 0.
5 nV-sec Low power: 3.
3 mW at 3 V 2.
7 V to 5.
5 V power supply −40°C to +105°C temperature range APPLICATIONS Optical transceivers Base-station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5686R/AD5685R/AD5684R, members of the nanoDAC+® family, are low power, quad, 16-/14-/12-bit buffered voltage output DACs.
The devices include a 2.
5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.
5 V (gain = 1) or 5 V (gain = 2).
All devices operate from a single 2.
7 V to 5.
5 V supply, are guaranteed monotonic by design, and exhibit less than 0.
1% FSR gain error and 1.
5 mV offset error performance.
The devices are available in a 3 mm × 3 mm LFCSP and a TSSOP package.
The AD5686R/AD5685R/AD5684R also incorporate a poweron reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remains there until a valid write takes place.
Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 µA at 3 V while in power-down mode.
The AD5686R/AD5685R/AD5684R employ a versatile SPI interface that operates at clock rates up to 50 MHz, and all devices contain a VLOGIC pin intended for 1.
8 V/3 V/5 V logic.
VLOGIC SCLK SYNC SDIN SDO FUNCTIONAL BLOCK DIAGRAM VDD GND...


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