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MM54HC161

Part Number	MM54HC161
Manufacturer	National Semiconductor
Description	Synchronous Binary Counter
Published	Feb 21, 2013
Detailed Description	74HC160 MM54 74HC161 MM54 74HC162 MM54 74HC163 January 1992 MM74HC160 Synchronous Decade Counter with Asynchronous Cle...
Datasheet	MM54HC161 PDF File

Overview

74HC160 MM54 74HC161 MM54 74HC162 MM54 74HC163 January 1992 MM74HC160 Synchronous Decade Counter with Asynchronous Clear MM54HC161 MM74HC161 Synchronous Binary Counter with Asynchronous Clear MM54HC162 MM74HC162 Synchronous Decade Counter with Synchronous Clear MM54HC163 MM74HC163 Synchronous Binary Counter with Synchronous Clear General Description The MM54HC160 MM74HC160 MM54HC161 MM74HC161 MM54HC162 MM74HC162 and MM54HC163 MM74HC163 synchronous presettable counters utilize advanced silicon-gate CMOS technology and internal look-ahead carry logic for use in high speed counting applications They offer the high noise immunity and low power consumption inherent to CMOS with speeds similar to low power Schottky TTL The ’HC160 and the ’HC162 are 4 bit decade counters and the ’HC161 and the ’HC163 are 4 bit binary counters All flip-flops are clocked simultaneously on the low to high transition (positive edge) of the CLOCK input waveform These counters may be preset using the LOAD input Presetting of all four flip-flops is synchronous to the rising edge of CLOCK When LOAD is held low counting is disabled and the data on the A B C and D inputs is loaded into the counter on the rising edge of CLOCK If the load input is taken high before the positive edge of CLOCK the count operation will be unaffected All of these counters may be cleared by utilizing the CLEAR input The clear function on the MM54HC162 MM74HC162 and MM54HC163 MM74HC163 counters are synchronous to the clock That is the counters are cleared on the positive edge of CLOCK while the clear input is held low The MM54HC160 MM74HC160 and MM54HC161 MM74HC161 counters are cleared asynchronously When the CLEAR is taken low the counter is cleared immediately regardless of the CLOCK Two active high enable inputs (ENP and ENT) and a RIPPLE CARRY (RC) output are provided to enable easy cascading of counters Both ENABLE inputs must be high to count The ENT input also enables the RC output When enabled the RC outputs a pos...

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