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GS8342T18E-200

Part Number	GS8342T18E-200
Manufacturer	GSI Technology
Description	36Mb SigmaCIO DDR-II Burst SRAM
Published	Feb 27, 2013
Detailed Description	Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 165-Bump BGA Commercial Temp Industrial Temp Features • Simulta...
Datasheet	GS8342T18E-200 PDF File

Overview

Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaCIO™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 2 Read and Write • 1.
8 V +100/–100 mV core power supply • 1.
5 V or 1.
8 V HSTL Interface • Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.
1 JTAG-compliant Boundary Scan • 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available • Pin-compatible with present 9Mb and 18Mb and future 72Mb and 144Mb devices 36Mb SigmaCIO DDR-II Burst of 2 SRAM 167 MHz–333 MHz 1.
8 V VDD 1.
8 V and 1.
5 V I/O Bottom View 165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array clock inputs, not differential inputs.
If the C clocks are tied high, t...

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