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H27UCG8U5BTR-BC

Hynix
Part Number H27UCG8U5BTR-BC
Manufacturer Hynix
Description 32Gb(4096M x 8bit) Legacy MLC NAND Flash
Published Jun 23, 2013
Detailed Description Preliminary H27UBG8T2BTR-BC Series 32Gb(4096M x 8bit) Legacy MLC NAND Flash F26 32Gb MLC NAND Flash Memory TSOP Legacy ...
Datasheet PDF File H27UCG8U5BTR-BC PDF File

H27UCG8U5BTR-BC
H27UCG8U5BTR-BC

Overview
Preliminary H27UBG8T2BTR-BC Series 32Gb(4096M x 8bit) Legacy MLC NAND Flash F26 32Gb MLC NAND Flash Memory TSOP Legacy http://www.
DataSheet4U.
net/ H27UBG8T2BTR-BC H27UCG8U5BTR-BC This document is a general product description and is subject to change without notice.
Hynix does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Rev 0.
7 / Jan.
2011 1 datasheet pdf - http://www.
DataSheet4U.
net/ Preliminary H27UBG8T2BTR-BC Series 32Gb(4096M x 8bit) Legacy MLC NAND Flash Document Title 32Gbit(4096M x 8bit) Legacy NAND Flash Memory Revision History Revision No.
0.
0 0.
1 ~ 0.
6 0.
7 Initial Draft 1st ~ 6th internal release Correct Figure4.
Array Organization(Page10) History Draft Date Oct.
13.
2010 Dec.
20.
2010 Jan.
03.
2011 Remark Preliminary Preliminary Preliminary http://www.
DataSheet4U.
net/ Rev 0.
7 / Jan.
2011 2 datasheet pdf - http://www.
DataSheet4U.
net/ Preliminary H27UBG8T2BTR-BC Series 32Gb(4096M x 8bit) Legacy MLC NAND Flash Product Feature ■ Multi Level Cell(MLC) Technology ■ NAND Interface - x8 bus width - Multiplexed address/ Data -Pin-out compatibility for all densities ■ Power Supply Voltage - VCC = 2.
7 V ~ 3.
6 V - VCCQ = 2.
7 V ~ 3.
6 V / 1.
7 V ~ 1.
95 V ■ Organization - Page size : (8K+640spare)bytes - Block size : (2048K+160K)bytes - Plane size : 1024blocks - Device size : 2048blocks ■ Page Read/Program Time - Random Read Time(tR): 90us(MLC), 40us(SLC) - Sequential Access: 20 ns (min.
) - Page Program Time: 1300us(MLC), 500us(SLC) - Parallel operations on both planes available, effectively halving program, read and erase time ■ Block Erase -Block Erase Time: 3.
5ms(Typ.
) ■ Multi-Plane Architecture - Two independent planes architecture - Parallel operations on both planes available, effectively halving program, read and erase time ■ Command Set - ONFI 2.
2 Compliant Command Set - Interleaved Copyback Program - Read Unique IDs ■ Package - Package type : TSOP - Chip count : SDP(1CE, Single) = 1stack DDP(2CE, Dual) = 2s...


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