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H5TC4G63MFR-xxA

Part Number	H5TC4G63MFR-xxA
Manufacturer	Hynix Semiconductor
Description	4Gb DDR3L SDRAM
Published	Sep 28, 2013
Detailed Description	4Gb DDR3L SDRAM 4Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TC4G43MFR-xxA H5TC4G83MFR-xxA H5TC4G63MFR-xx...
Datasheet	H5TC4G63MFR-xxA PDF File

Overview

4Gb DDR3L SDRAM 4Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TC4G43MFR-xxA H5TC4G83MFR-xxA H5TC4G63MFR-xxA * SK hyix Semiconductor reserves the right to change products or specifications without Rev.
1.
0 / Nov.
2012 1 Free Datasheet http://www.
datasheet4u.
com/ Revision History Revision No.
0.
1 0.
2 0.
3 0.
4 0.
5 1.
0 History Initial Release Ballout typo correction Package Dimension correction Added IDD Specification Added IDD Specification(x16) Latest JEDEC Spec Updated Draft Date Apr.
2011 May.
2011 Jun.
2011 Aug.
2011 Nov.
2011 Nov.
2012 Remark Rev.
1.
0 / Nov.
2012 2 Free Datasheet http://www.
datasheet4u.
com/ Description The H5TC4G43MFR-xxA, H5TC4G83MFR-xxA and H5TC4G63MFR-xxA are a 4Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.
35V.
DDR3L SDRAM provides backward compatibility with the 1.
5V DDR3 based environment without any changes.
(Please refer to the SPD information for details.
) SK hynix 4Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Device Features and Ordering Information FEATURES • VDD=VDDQ=1.
35V + 0.
100 / - 0.
067V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • Average Refresh Cycle (Tcase of 0 oC~ 95 oC) - 7.
8 µs at 0oC ~ 85 oC - 3.
9 µs at 85oC ~ 95 oC • On chip DLL align DQ, DQS and DQS transition with CK  • JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA (x16) transition • DM masks write data-in at the both rising and falling  edges of the data strobe • All addresses and control inputs...

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H5TC4G63MFR-xxA 4Gb DDR3L SDRAM - Hynix Semiconductor

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