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AK8443

AKM
Part Number AK8443
Manufacturer AKM
Description 16bit 30MSPS video ADC
Published Oct 10, 2013
Detailed Description [AK8443] AK8443 16bit 30MSPS video ADC with CCD/CIS interface Features … CCD I/F Channel number D-Range CDS circuit ADC...
Datasheet PDF File AK8443 PDF File

AK8443
AK8443

Overview
[AK8443] AK8443 16bit 30MSPS video ADC with CCD/CIS interface Features … CCD I/F Channel number D-Range CDS circuit ADC Max.
Conversion Rate Resolution Offset DAC Range Resolution PGA Range Resolution Output format Power supply CPU I/F Power consumption Operation Temperature: Package VCLP Black Correction 3ch (2ch.
) 1.
764Vpp / 2.
341Vpp ( typ.
) Pos.
/Neg.
polarity 30MSPS (10MSPS/ch) 16bit (straight binary code) ±321mV (normal input range) 8bit 0dB~22dB 7bit 8bit x 2 Æ 16bit or 4bit x 4 Æ 16bit 3.
3V±0.
3V 3 Wire Serial Interface 365 mW (typ.
) 0°C~70°C 28pin QFN with radiation PAD in solder side AVDD AVSS VRP VRN VCOM … … … … … … … … … Reference Voltage PGA sign+17b 16bit ADC 3:1 MUX LIMIT ＋ Output Control 7b Reg.
PGA 8b or 4b D2∼D7 D1(SDATA) D0(SDCLK) CCDIN0 CDS / Clamp 8bit DAC CCDIN1 CDS / Clamp 8bit DAC 7b Reg.
PGA CCDIN2 CDS / Clamp 8bit DAC CKGEN 7b Reg .
Serial I/F SDENB RESETB SHD SHR MCLK DVDD DVSS MS1280-E-00 1 2011/8 Free Datasheet http://www.
datasheet4u.
com/ [AK8443] Circuit Block „ Clamp, CDS Block The clamp circuit and correlated double sample circuits are provided for CCD output signal.
In CDS mode, the difference between the feed threw level of signal and the data level is sampled.
In clamp mode, the difference between the internal reference VCLP and the data level of signal is sampled.
Clamp pull the feed threw level into VCLP level when SHR is high.
„ Black Correction Circuit to add an offset voltage to the sampled signal level.
Voltage range of DAC which generates Offset is ±321 mV(typ.
) and its resolution is 8 bit.
„ MUX Block MUX is a select switch that selects one signal from three ADC output signals sequentially.
The AK8443 has 2-channel mode and 3-channel mode.
Each mode is selected by control register.
„ ADC Block The ADC coverts PGA output signal to digital data.
The resolution is 16-bit and the maximum conversion rate is 30MSPS.
The output code is straight binary.
The output data corresponding to black is 0000h, and ...


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