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MCM63F919

Motorola
Part Number MCM63F919
Manufacturer Motorola
Description 256K x 36 and 512K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
Published Nov 6, 2013
Detailed Description MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63F837/D Product Previ...
Datasheet PDF File MCM63F919 PDF File

MCM63F919
MCM63F919


Overview
MOTOROLA Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63F837/D Product Preview 256K x 36 and 512K x 18 Bit Flow–Through BurstRAM Synchronous Fast Static RAM The MCM63F837 and MCM63F919 are 8M–bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache for the PowerPC™ and other high performance microprocessors.
The MCM63F837 (organized as 256K words by 36 bits) and the MCM63F919 (organized as 512K words by 18 bits) are fabricated in Motorola’s high performance silicon gate CMOS technology.
Synchronous design allows precise cycle control with the use of an external clock (K).
Addresses (SA), data inputs (DQx), and all control signals except output enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K) controlled through positive–edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins.
Subsequent burst addresses can be generated internally by the MCM63F837 and MCM63F919 (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the clock (K) input.
This feature eliminates complex off–chip write pulse generation and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes.
The bytes are designated as “a”, “b”, etc.
SBa controls DQa, SBb controls DQb, etc.
Individual bytes are written if the selected byte writes SBx are asserted with SW.
All bytes are written if either SGW is asserted or if all SBx and SW are asserted.
For read cycles, a flow–through SRAM allows output data to simply flow freely from the memory array.
The MCM63F837 and MCM63F919 operate from a 3.
3 V core power supply and all ou...


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