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IDT71P73804

Part Number	IDT71P73804
Manufacturer	IDT
Description	18Mb Pipelined DDRII SRAM
Published	Nov 9, 2013
Detailed Description	18Mb Pipelined DDR™II SRAM Burst of 4 Features ◆ ◆ ◆ ◆ ◆ IDT71P73204 IDT71P73104 IDT71P73804 IDT71P73604 Description T...
Datasheet	IDT71P73804 PDF File

Overview

18Mb Pipelined DDR™II SRAM Burst of 4 Features ◆ ◆ ◆ ◆ ◆ IDT71P73204 IDT71P73104 IDT71P73804 IDT71P73604 Description The IDT DDRIITM Burst of four SRAMs are high-speed synchronous memories with a double-data-rate (DDR), bidirectional data port.
This scheme allows maximization on the bandwidth on the data bus by passing two data items per clock cycle.
The address bus operates at less than single data rate speeds,allowing the user to fan out addresses and ease system design while maintaining maximum performance on data transfers.
The DDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance.
All interfaces of the DDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface.
The interface can be scaled to higher voltages (up to 1.
9V) to interface with 1.
8V systems if necessary.
The device has a VDDQ and a separate Vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.
8V VDD.
The output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines.
◆ ◆ ◆ ◆ ◆ ◆ ◆ 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512Kx36) Common Read and Write Data Port Dual Echo Clock Output 4-Word Burst on all SRAM accesses Multiplexed Address Bus One Read or One Write request per two clock cycles.
DDR (Double Data Rate) Data Bus - Four word bursts data per two clock cycles Depth expansion through Control Logic HSTL (1.
5V) inputs that can be scaled to receive signals from 1.
4V to 1.
9V.
Scalable output drivers Can drive HSTL, 1.
8V TTL or any voltage level from 1.
4V to 1.
9V.
Output Impedance adjustable from 35 ohms to 70 ohms 1.
8V Core Voltage (VDD) JTAG Interface 165-ball, 1.
0mm pitch, 13mm x 15mm fBGA Package Functional Block Diagram DATA REG (Note1) WRITE DRIVER LD RW BWx (Note3) CTRL LOGIC 18M MEMORY ARRAY (Note4) OUTPUT SELECT SENSE AMPS OUTPUT REG ...

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