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IC61S25636T

Integrated Circuit Solution
Part Number IC61S25636T
Manufacturer Integrated Circuit Solution
Description 8Mb SyncBurst Pipelined SRAM
Published Nov 15, 2013
Detailed Description IC61S25632T/D IC61S25636T/D IC61S51218T/D Document Title 8Mb SyncBurst Pipelined SRAM Revision History Revision No 0A 0...
Datasheet PDF File IC61S25636T PDF File

IC61S25636T
IC61S25636T

Overview
IC61S25632T/D IC61S25636T/D IC61S51218T/D Document Title 8Mb SyncBurst Pipelined SRAM Revision History Revision No 0A 0B History Initial Draft 1.
Move the FT pin for user-configurable Flow throught or pipelineed operation, That pin can be NC or connected to VCC for pipelined operation.
Refer to Pin configuration.
2.
Revise the power supply charaetoristics at page 12 3.
Resive the tKQ of 250 MHZ from 2.
5ns to 3ns.
4.
Move the 100 MHZ speed grade.
Draft Date Remark September 24,2001 August 13,2002 The attached datasheets are provided by ICSI.
Integrated Circuit Solution Inc reserve the right to change the specifications and products.
ICSI will answer to your questions about device.
If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002 1 Free Datasheet http://www.
datasheet4u.
com/ IC61S25632T/D IC61S25636T/D IC61S51218T/D 256K x 32, 256K x 36, 512K x 18 8Mb S/DCD SYNCBURST Pipelined SRAMs FEATURES • • • • • • • • • • • • • • • Pipeline Mode operation Single/Dual Cycl Deselect User-selectable Output Drive Strength with XQ Mode Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Pentium™ or linear burst sequence control using MODE input Common data inputs and data outputs JEDEC 100-Pin TQFP and 119-pin PBGA package Single +3.
3V, +10%, –5% core power supply Power-down snooze mode 2.
5V or 3.
3V I/O Supply Snooze MODE for reduced-power standby T version (three chip selects) D version (two chip selects) Controls All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.
Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins.
Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order, Linear burst is achieve...


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