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CY7C1511JV18

Cypress Semiconductor
Part Number CY7C1511JV18
Manufacturer Cypress Semiconductor
Description 72-Mbit QDR-II SRAM 4-Word Burst Architecture
Published Dec 3, 2013
Detailed Description CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 72-Mbit QDR™-II SRAM 4-Word Burst Architecture Features ■ Config...
Datasheet PDF File CY7C1511JV18 PDF File

CY7C1511JV18
CY7C1511JV18

Overview
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 72-Mbit QDR™-II SRAM 4-Word Burst Architecture Features ■ Configurations CY7C1511JV18 – 8M x 8 CY7C1526JV18 – 8M x 9 CY7C1513JV18 – 4M x 18 CY7C1515JV18 – 2M x 36 Separate independent read and write data ports ❐ Supports concurrent transactions 300 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches Echo clocks (CQ and CQ) simplify data capture in high speed systems Single multiplexed address input bus latches address inputs for read and write ports Separate port selects for depth expansion Synchronous internally self-timed writes QDR-II operates with 1.
5 cycle read latency when the Delay Lock Loop (DLL) is enabled Operates similar to a QDR-I device with 1 cycle read latency in DLL off mode Available in x8, x9, x18, and x36 configurations Full data coherency, providing most current data Core VDD = 1.
8 (± 0.
1V); IO VDDQ = 1.
4V to VDD Available in 165-ball FBGA package (15 x 17 x 1.
4 mm) Offered in both Pb-free and non Pb-free packages Variable drive HSTL output buffers JTAG 1149.
1 compatible test access port Delay Lock Loop (DLL) for accurate data placement ■ ■ ■ ■ Functional Description The CY7C1511JV18, CY7C1526JV18, CY7C1513JV18, and CY7C1515JV18 are 1.
8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture.
QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array.
The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.
QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus that exists with co...


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