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HYB18TC1G160BF

Qimonda
Part Number HYB18TC1G160BF
Manufacturer Qimonda
Description 1-Gbit Double-Data-Rate-Two SDRAM
Published Dec 5, 2013
Detailed Description July 2007 HYB18T C1G 80 0 BF HYB18T C1G 16 0 BF 1-Gbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products ...
Datasheet PDF File HYB18TC1G160BF PDF File

HYB18TC1G160BF
HYB18TC1G160BF

Overview
July 2007 HYB18T C1G 80 0 BF HYB18T C1G 16 0 BF 1-Gbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev.
1.
21 Free Datasheet http://www.
datasheet4u.
com/ Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM HYB18TC1G800BF, HYB18TC1G160BF Revision History: 2007-07, Rev.
1.
21 Page All 14 136 Subjects (major changes since last revision) Adapted internet edition Corrected Table 9: Added Ball B2 and B8 Corrected package outline Editorial changes Previous Revision: 2007-03, Rev.
1.
1 Previous Revision: 2007-03, Rev.
1.
2 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to: techdoc@qimonda.
com qag_techdoc_rev400 / 3.
2 QAG / 2006-07-21 02282007-F8UP-4HSU 2 Free Datasheet http://www.
datasheet4u.
com/ Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 1 Overview This chapter gives an overview of the 1-Gbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics.
1.
1 Features The 1-Gbit Double-Data-Rate-Two SDRAM offers the following key features: • Off-Chip-Driver impedance adjustment (OCD) and On• 1.
8 V ± 0.
1 V Power Supply 1.
8 V ± 0.
1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality.
• DRAM organizations with 8 and 16 data in/outputs • Auto-Precharge operation for read and write bursts • Double Data Rate architecture: two data transfers per • Auto-Refresh, Self-Refresh and power saving PowerDown modes clock cycle four internal banks for concurrent operation • Average Refresh Period 7.
8 µs at a TCASE lower than • Programmable CAS Latency: 3, 4, 5 and 6 85 °C, 3.
9 µs between 85 °C and 95 °C • Programmable Burst Length: 4 and 8 • Programmable self refresh rate via EMRS2 setting • Differential clock inputs (CK and CK) • Pr...


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