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HEF40160B

NXP
Part Number HEF40160B
Manufacturer NXP
Description 4-bit synchronous decade counter with asynchronous reset
Published Mar 23, 2005
Detailed Description INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family ...
Datasheet PDF File HEF40160B PDF File

HEF40160B
HEF40160B

Overview
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF40160B MSI 4-bit synchronous decade counter with asynchronous reset Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 4-bit synchronous decade counter with asynchronous reset DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0 to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count enable trickle (CET)), buffered outputs from all four bit positions (O0 to O3) and a terminal count output (TC).
Operation is fully synchronous (except for the MR input) and occurs on the LOW to HIGH transition of CP.
When PE is LOW, the next LOW to HIGH transition of CP loads data into the counter from P0 to P3 regardless of the levels of CEP and CET inputs.
HEF40160B MSI When PE is HIGH, the next LOW to HIGH transition of CP advances the counter to its next state only if both CEP and CET are HIGH; otherwise, no change occurs in the state of the counter.
TC is HIGH when the state of the counter is 9 (O0 = O3 = HIGH, O1 = O2 = LOW) and when CET is HIGH.
A LOW on MR sets all outputs (O0 to O3 and TC) LOW, independent of the state of all other inputs.
Multistage synchronous counting is possible without additional components by using a carry look-ahead counting technique; in this case, TC is used to enable successive cascaded stages.
CEP, CET and PE must be stable only during the set-up time before the LOW to HIGH transition of CP.
Fig.
1 Functional diagram.
FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 This text is here in white to force landscape pages to be rotated correctly when browsing ...


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