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ICS9LPRS501

IDT
Part Number ICS9LPRS501
Manufacturer IDT
Description 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Published Apr 22, 2014
Detailed Description Datasheet 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Recommended Application: CK505...
Datasheet PDF File ICS9LPRS501 PDF File

ICS9LPRS501
ICS9LPRS501

Overview
Datasheet 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Recommended Application: CK505 compliant clock with fully integrated voltage regulator and Internal series resistor on differential outputs, PCIe Gen 1 compliant ICS9LPRS501 Key Specifications: • • • • CPU outputs cycle-cycle jitter < 85ps SRC output cycle-cycle jitter < 125ps PCI outputs cycle-cycle jitter < 250ps +/- 100ppm frequency accuracy on CPU & SRC clocks Output Features: • • • • • • • • 2 - CPU differential low power push-pull pairs 10 - SRC differential low power push-pull pairs 1 - CPU/SRC selectable differential low power push-pull pair 1 - SRC/DOT selectable differential low power push-pull pair 5 - PCI, 33MHz 1 - PCI_F, 33MHz free running 1 - USB, 48MHz 1 - REF, 14.
318MHz • • • • • Features/Benefits: Does not require external pass transistor for voltage regulator Integrated series resistors on differential outputs, Zo=50Ω Supports spread spectrum modulation, default is 0.
5% down spread Uses external 14.
318MHz crystal, external crystal load caps are required for frequency tuning One differential push-pull pair selectable between SRC and two single-ended outputs Table 1: CPU Frequency Select Table FSLC B0b7 0 0 0 0 1 1 1 1 2 TSSOP Pin Configuration USB MHz DOT MHz FSLB B0b6 0 0 1 1 0 0 1 1 1 FSLA B0b5 0 1 0 1 0 1 0 1 1 CPU MHz 266.
66 133.
33 200.
00 166.
66 333.
33 100.
00 400.
00 SRC MHz PCI MHz REF MHz 100.
00 33.
33 14.
318 48.
00 96.
00 Reserved 1.
FSLA and FSLB are low-threshold inputs.
Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2.
FSLC is a three-level input.
Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values.
PCI0/CR#_A 1 VDDPCI 2 PCI1/CR#_B 3 PCI2/TME 4 PCI3 5 PCI4/SRC5_EN 6 PCI_F5/ITP_EN 7 GNDPCI 8 VDD48 9 USB_48MHz/FSLA 10 GND48 11 VDD96_IO 12 DOTT_96/SRCT0 13 DOTC_...


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