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AK5406

Part Number	AK5406
Manufacturer	AKM
Description	80MSPS Triple ADC
Published	May 11, 2014
Detailed Description	ASAHI KASEI [AK5406] AK5406 80MSPS Triple ADC for Displays General Description The AK5406 is an RGB Graphic & D-termin...
Datasheet	AK5406 PDF File

Overview

ASAHI KASEI [AK5406] AK5406 80MSPS Triple ADC for Displays General Description The AK5406 is an RGB Graphic & D-terminal Signal Process Device in which integrates 10-Bit 80Mhz AD Converters.
The Device has On-Chip 3 Channels ADCs , Voltage Reference circuit, Programmable Gain Offset Amplifiers and Black Loop Function which automatically sustains Clamp Level to an arbitrarily set value.
Features • • • • • • ADCs 80 MSPS max.
(Inte rnally • Power Down function 10-bit, Output is reduced to 8-bit) • Low Power Dissipation 0.
5V ~ 1.
0V input signal range • 3.
3V ± 0.
3V power supply Black Loop (Automatic Offset adjust) • CMOS function • -40℃ to 85℃ Low Clock Jitter • Package 80-LQFP On-Chip SYNC Separation function Pedestal Clamp and Mid-Point Clamp function BIAS BYPASS VREF AVDD AVSS PVDD DVDD DVSS RIN CLAMP PGA 10bit ADC 10 BLACK LOOP 8 ROUT7~0 8 GIN The same as Rch GOUT7~0 BIN The same as Rch 8 BOUT7~0 CLAMP COAST SOGIN VSYNC HSYNC TEST2 Sync Processing DTCLK SOGOUT VSYNCO HSYNCO Control Serial I/F FLT TEST SDA SCL A0 RESET Fig.
1 Block Diagram MS0592-E-01 1 2008/07 http://www.
Datasheet4U.
com ASAHI KASEI [AK5406] ■ Functional Block Description Table 1 : Block Description block Function CLAMP To Clamp Pedestal level of input signal during Clamp period.
PGA Programmable Gain Amplifier.
It has 8-bit resolution.
Full-scale input range of ADC can be pre-set from 0.
5V to 1V.
ADC 10-bit 80 MSPS AD Converter.
BLACK LOOP A loop to settle Pedestal level to the Black set value.
Can be disable by register setting.
VREF To generate internal reference voltage.
Control Serial I/F Control register with I2C Interface (400KHz).
Sync Processing To generate timing signals such as ADC operating clock, from Horizontal / Vertical SYNC signal inputs.
SLICER Comparator to slice SYNC signal part in SYNC-ON-Green signal.
PLL PLL to generate Pixel Clock from Horizontal SYNC signal COAST To generate Coast signal from VSYNC.
GEN CLAMP To generate Clamp signal from HSYNC.
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