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NB3V8312C

Part Number	NB3V8312C
Manufacturer	ON Semiconductor
Description	Ultra-Low Jitter Low Skew 1:12 LVCMOS - LVTTL Fanout Buffer
Published	May 14, 2014
Detailed Description	NB3V8312C Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout Buffer The NB3V8312C is a high performance, low skew L VCM...
Datasheet	NB3V8312C PDF File

Overview

NB3V8312C Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout Buffer The NB3V8312C is a high performance, low skew L VCMOS fanout buffer which can distribute 12 ultra −low jitter clocks from an LVCMOS/LVTTL input up to 250 MHz.
The 12 LVCMOS output pins drive 50 W series or parallel terminated transmission lines.
The outputs can also be disabled to a high impedance (tri−stated) via the OE input, or enabled when High.
The NB3V8312C provides an enable input, CLK_EN pin, which synchronously enables or disables the clock outputs while in the LOW state.
Since this input is internally synchronized to the input clock, changing only when the input is LOW , potential output glitching or runt pulse generation is eliminated.
Separate V DD core and V DDO output supplies allow the output buffers to operate at the same supply as the V DD (V DD = V DDO) or from a lower supply voltage.
Compared to single −supply operation, dual supply operation enables lower power consumption and output−level compatibility.
The V DD core supply voltage can be set to 3.
3 V , 2.
5 V or 1.
8 V, while the VDDO output supply voltage can be set to 3.
3 V , 2.
5 V, or 1.
8 V, with the constraint that VDD ≥ VDDO.
This buffer is ideally suited for various networking, telecom, server and storage area networking, RRU LO reference distribution, medical and test equipment applications.
Features http://onsemi.
com 1 LQFP−32 FA SUFFIX CASE 873A VDDO VDD GND RPU CLK_EN D Q 32 QFN32 MN SUFFIX CASE 488AM Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 CLK RPD • Power Supply Modes: • • • • • • • • • • VDD (Core) / VDDO (Outputs) 3.
3 V / 3.
3 V 3.
3 V / 2.
5 V 3.
3 V / 1.
8 V 2.
5 V / 2.
5 V 2.
5 V / 1.
8 V 1.
8 V / 1.
8 V 250 MHz Maximum Clock Frequency Accepts LVCMOS, LVTTL Clock Inputs LVCMOS Compatible Control Inputs 12 LVCMOS Clock Outputs Synchronous Clock Enable Output Enable to High Z State Control 150 ps Max.
Skew Between Outputs Temp.
Range −40°C to +85°C 32−pin LQFP and QFN Packages These are Pb−Free Devices OE RPU Figure ...

Similar Datasheet

NB3V8312C Ultra-Low Jitter Low Skew 1:12 LVCMOS - LVTTL Fanout Buffer - ON Semiconductor

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