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ADSP-BF504F

Analog Devices
Part Number ADSP-BF504F
Manufacturer Analog Devices
Description Blackfin Embedded Processor
Published May 25, 2014
Detailed Description Blackfin Embedded Processor ADSP-BF504/ADSP-BF504F/ADSP-BF506F FEATURES Up to 400 MHz high performance Blackfin processo...
Datasheet PDF File ADSP-BF504F PDF File

ADSP-BF504F
ADSP-BF504F


Overview
Blackfin Embedded Processor ADSP-BF504/ADSP-BF504F/ADSP-BF506F FEATURES Up to 400 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring Accepts a range of supply voltages for internal and I/O operations.
See Operating Conditions on Page 26 Internal 32M bit flash (available on ADSP-BF504F and ADSP-BF506F processors) Internal ADC (available on ADSP-BF506F processor) Off-chip voltage regulator interface 88-lead (12 mm × 12 mm) LFCSP package for ADSP-BF504 and ADSP-BF504F processors 120-lead (14 mm × 14 mm) LQFP package for ADSP-BF506F processor PERIPHERALS Two 32-bit up/down counters with rotary support Eight 32-bit timers/counters with PWM support Two 3-phase 16-bit center-based PWM units 2 dual-channel, full-duplex synchronous serial ports (SPORTs), supporting eight stereo I2S channels 2 serial peripheral interface (SPI) compatible ports 2 UARTs with IrDA support Parallel peripheral interface (PPI), supporting ITU-R 656 video data formats Removable storage interface (RSI) controller for MMC, SD, SDIO, and CE-ATA Internal ADC with 12 channels, 12 bits, and up to 2 MSPS ADC controller module (ACM), providing a glueless interface between Blackfin processor and internal or external ADC Controller Area Network (CAN) controller 2-wire interface (TWI) controller 12 peripheral DMAs 2 memory-to-memory DMA channels Event handler with 52 interrupt inputs 35 general-purpose I/Os (GPIOs), with programmable hysteresis Debug/JTAG interface On-chip PLL capable of frequency multiplication MEMORY F w C r e .
n a ww WATCHDOG TIMER JTAG TEST AND EMULATION INTERRUPT CONTROLLER L1 DATA MEMORY 16 DCB DEB DMA CONTROLLER MEMORY PORT FLASH CONTROL ua PERIPHERAL ACCESS BUS DMA ACCESS BUS BOOT ROM 68K bytes of L1 SRAM (processor core-accessible) memory (See Table 1 on Page 3 for L1 and L3 m...


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