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HD151012

Hitachi Semiconductor
Part Number HD151012
Manufacturer Hitachi Semiconductor
Description 8-bit Binary Programmable Counter with Synchronous Preset Enable
Published Mar 23, 2005
Detailed Description HD151012 8-bit Binary Programmable Counter with Synchronous Preset Enable ADE-205-132 (Z) Preliminary 1st. Edition Mar....
Datasheet PDF File HD151012 PDF File

HD151012
HD151012

Overview
HD151012 8-bit Binary Programmable Counter with Synchronous Preset Enable ADE-205-132 (Z) Preliminary 1st.
Edition Mar.
1996 Description The HD151012 has 8-bit binary down counter and D-type Flip Flop.
The counter can set up to max 256 counts and synchronous preset (SPE) input can preset the data.
When the count value is 0, the next clock pulse presets the data to invert the output.
D-type Flip Flop takes the counter output as clock pulse, whose data is transferred to output at the rise edge.
It is applied to generate AC signal for STN type liquid crystal and general-use divider.
Features • High speed operation tpd (CLK or CLK to Q) = 35 ns (typ) • High output current Fanout of 10 LS TTL Loads • Wide operating voltage VCC = 2 to 6 V • Low supply current (Ta = 25°C) ICC (Static) = 4 µA (max) HD151012 Function Table Control Inputs CLR H X L H PR H X H L SPE H L — — Mode Generally count Synchronous preset Initialize of Q output Initialize of Q output Operation Description Down count at the rise edge of clock (CLK) Down count at the fall edge of clock (CLK) Jn data is preset at the rise of clock (CLK), the fall of clock (CLK) Initialize of Q = “L” Initialize of Q = “H” Notes: 1.
Synchronous preset ( SPE) input can set max 256 down counts.
2.
When the count value is 0, the next clock pulse presets the data to invert the output.
3.
CLR and PR inputs initialize output state.
H : High level L : Low level X : Immaterial — : Irrespective of condition Pin Arrangement J0 1 J1 2 J2 3 J3 4 J4 5 J5 6 J6 7 GND 8 16 VCC 15 CLK 14 CLK 13 Q 12 PR 11 SPE 10 CLR 9 J7 (Top view) 2 HD151012 Pin Description Pin Name Input pins J0 to J7 CLK, CLK SPE PR CLR Output pins Q Pin Description Count data input for option Clock inputs Preset input for Jn data Preset input for D-type Flip Flop (Initialize “L” at Q output) Clear input for D-type Flip Flop (Initialize “H” at Q output) Output for D-type Flip Flop CLK : Rise edge trigger CLK : Fall edge trigger Absolute Maximum Ratings Item Su...


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