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HD74ALVCH16270

Hitachi Semiconductor
Part Number HD74ALVCH16270
Manufacturer Hitachi Semiconductor
Description 12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs
Published Mar 23, 2005
Detailed Description HD74ALVCH16270 12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs ADE-205-137 (Z) Preliminary 1st. Edition ...
Datasheet PDF File HD74ALVCH16270 PDF File

HD74ALVCH16270
HD74ALVCH16270


Overview
HD74ALVCH16270 12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs ADE-205-137 (Z) Preliminary 1st.
Edition May 1996 Description The HD74ALVCH16270 is used in applications where data must be transferred from a narrow high speed bus to a wide lower frequency bus.
The device provides synchronous data exchange between the two ports.
Data is stored in the internal registers on the low to high transition of the clock (CLK) input when the appropriate CLKEN inputs are low.
The select (SEL) line selects 1B or 2B data for the A outputs.
For data transfer in the A to B direction, a two stage pipeline is provided in the A to 1B path, with a single storage register in the A to 2B path.
Proper control of the CLKENA inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port.
Data flow is controlled by the active low output enables (OEA , OEB).
The control terminals are registered to synchronize the bus direction changes with CLK.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Features • VCC = 2.
3 V to 3.
6 V • Typical VOL ground bounce < 0.
8 V (@VCC = 3.
3 V, Ta = 25°C) • Typical VOH undershoot > 2.
0 V (@VCC = 3.
3 V, Ta = 25°C) • High output current ±24 mA (@VCC = 3.
0 V) • Bus hold on data inputs eliminates the need for external pullup / pulldown resistors HD74ALVCH16270 Function Table Inputs CLK ↑ ↑ ↑ ↑ OEA H H L L OEB H L H L Outputs A Z Z Active Active 1B, 2B Z Active Z Active Output enable Inputs CLKENA1 L L L L H H H CLKENA2 H H L L L L H CLK ↑ ↑ ↑ ↑ ↑ ↑ X A L H L H L H X Outputs 1B L *2 2B 2B0 2B0 L H *1 *1 *1 *1 *1 H *2 L *2 H *2 1B0 1B0 1B0 L H 2B0 *1 A-to-B storage (OEB = L) Inputs CLKEN1B H X L L X X CLKEN2B X H X X L L CLK X X ↑ ↑ ↑ ↑ SEL H L H H L L 1B X X L H X X 2B X X X X L H Output A A0 A0 L H L H *1 *1 B-to-A storage (OEA = L) H : High level L : Low level X : Immaterial Z : High impedance ↑ : Low to high transition Notes: 1.
Output level befo...


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