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HD74ALVCH162820

Hitachi Semiconductor
Part Number HD74ALVCH162820
Manufacturer Hitachi Semiconductor
Description 3.3-V 10-bit Flip Flops with Dual Outputs and 3-state Outputs
Published Mar 23, 2005
Detailed Description HD74ALVCH162820 3.3-V 10-bit Flip Flops with Dual Outputs and 3-state Outputs ADE-205-185B (Z) 3rd. Edition December 19...
Datasheet PDF File HD74ALVCH162820 PDF File

HD74ALVCH162820
HD74ALVCH162820

Overview
HD74ALVCH162820 3.
3-V 10-bit Flip Flops with Dual Outputs and 3-state Outputs ADE-205-185B (Z) 3rd.
Edition December 1999 Description The HD74ALVCH162820 flip flops are edge triggered D-type flip flops.
On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs.
A buffered output enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high impedance state.
In the high impedance state, the outputs neither load nor drive the bus lines significantly.
The high impedance state and increased drive provide the capability to drive bus line without need for interface or pullup components.
OE does not affect the internal operations of the flip flops.
Old data can be retained or new data can be entered while the outputs are in the high impedance state.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
All outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce overshoot and undershoot.
Features • VCC = 2.
3 V to 3.
6 V • Typical VOL ground bounce < 0.
8 V (@VCC = 3.
3 V, Ta = 25°C) • Typical VOH undershoot > 2.
0 V (@VCC = 3.
3 V, Ta = 25°C) • High output current ±12 mA (@V CC = 3.
0 V) • Bus hold on data inputs eliminates the need for external pullup / pulldown resistors • All outputs have equivalent 26 Ω series resistors, so no external resistors are required.
HD74ALVCH162820 Function Table Inputs OEn L L L H *2 Output Q CLK ↑ ↑ L X D H L X X H L Q0 *1 Z H : High level L : Low level X : Immaterial Z : High impedance ↑ : Low to high transition Notes: 1.
Output level before the indicated steady state input conditions were established.
2.
n = 1, 2 2 HD74ALVCH162820 Pin Arrangement 1OE 1 1Q1 2 1Q2 3 GND 4 2Q1 5 2Q2 6 VCC 7 3Q1 8 3Q2 9 4Q1 10 GND 11 4Q2 12 5Q1 13 5Q2 14 6Q1 15 6Q2 16 7Q1 17 GND 18 7Q2 19 8Q1 20 8Q2 21 VCC 22 9Q1 23 9Q2 24 GND 25 10Q1 26 10Q2 27 2OE 28 56 CLK 55 D1 54 NC 53 GND 52 D2...


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