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HD74HC323

Part Number	HD74HC323
Manufacturer	Hitachi Semiconductor
Description	8-bit Universal Shift/Storage Register (with 3-state Outputs)
Published	Mar 23, 2005
Detailed Description	HD74HC323 8-bit Universal Shift/Storage Register (with 3-state Outputs) Description This eight-bit universal register f...
Datasheet	HD74HC323 PDF File

Overview

HD74HC323 8-bit Universal Shift/Storage Register (with 3-state Outputs) Description This eight-bit universal register features multiplexed I/O ports to achieve full eight bit data handling in a single 20-pin package.
HD74HC323 applications are as stacked or push-down registers, buffer storage, and accumulator registers.
Two function-select inputs and two output control inputs can be used to choose the modes of operation listed in the function table.
Synchronous parallel loading is accomplished by taking both function-select lines S0 and S1 high.
This places the three-state outputs in a high-impedance state, which permits data that is applied on the I/O ports to be clocked into the register.
Reading out of this register can be accomplished while the outputs are enabled in any mode.
The clear function is synchronous, and a low level at the clear input clears the register on the next low-to-high transition of the clock.
Features • • • • • High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HC323 Function Table Inputs Function Select Mode Clear Clear L L Hold H H Shift Right Shift Left Load H H H H H S1 X L L X L L H H H S0 L X L X H H L L H Output Control G1† G2† L L L L L L L L X L L L L L L L L X X L Serial Inputs/Outputs Outputs QH’ L L QH0 QH0 QGn QGn H L h Clock SL SR A/QA B/QB C/QC D/QD E/QE F/QF G/Q G H/QH QA’ X X X X X X H L X X X X X H L X X X L L QA0 QA0 H L QBn QBn a L L QB0 QB0 QAn QAn QCn QCn b L L QC0 QC0 QBn QBn QDn QDn c L L QD0 QD0 QCn QCn QEn QEn d L L QE0 QE0 QDn QDn QFn QFn e L L QF0 QF0 QEn QEn QGn QGn f L L QG0 QG0 QFn QFn QHn QHn g L L QH0 QH0 QGn QGn H L h L L QA0 QA0 H L QBn QBn a a .
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h = the level of the steady-state input at A through H, respectively.
These data are loaded into the flipflops while the flip-flop outputs are isolated from the inp...

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