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HD74LV165A

Hitachi Semiconductor
Part Number HD74LV165A
Manufacturer Hitachi Semiconductor
Description Parallel-Load 8-bit Shift Register
Published Mar 23, 2005
Detailed Description HD74LV165A Parallel-Load 8-bit Shift Register ADE-205-267 (Z) 1st Edition March 1999 Description The HD74LV165A is 8-bi...
Datasheet PDF File HD74LV165A PDF File

HD74LV165A
HD74LV165A

Overview
HD74LV165A Parallel-Load 8-bit Shift Register ADE-205-267 (Z) 1st Edition March 1999 Description The HD74LV165A is 8-bit serial shift register shifts data from QA to QH when clocked.
Parallel inputs to each stage are enabled by a low level at the Shift/Load input.
Also included is a gated clock input and a complementary output from the eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit function.
Holding either of the clock inputs high inhibits clocking, and high enables the other clock input.
Data transfer occurs on the positive going edge of the clock.
Parallel loading is inhibited as long as the Shift/Load input is high.
When taken low, data at the parallel inputs is loaded directly into the register independent of the state of the clock.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.
g.
, notebook computers), and the low-power consumption extends the battery life.
Features • • • • • • VCC = 2.
0 V to 5.
5 V operation All inputs VIH (Max.
) = 5.
5 V (@VCC = 0 V to 5.
5 V) All outputs VO (Max.
) = 5.
5 V (@VCC = 0 V) Typical VOL ground bounce < 0.
8 V (@VCC = 3.
3 V, Ta = 25°C) Typical VOH undershoot > 2.
3 V (@VCC = 3.
3 V, Ta = 25°C) Output current ±6 mA (@VCC = 3.
0 V to 3.
6 V), ±12 mA (@VCC = 4.
5 V to 5.
5 V) HD74LV165A Function Table Inputs SH/LD L H H H H H H CLK INH X L L H X ↑ ↑ CLK X ↑ ↑ X H L L SER X H L X X H L A .
.
.
H a .
.
.
h X X X X X X Internal Outputs QA a H L QA0 QA0 H L QB b QAn QAn QB0 QB0 QAn QAn Output QH h QGn QGn QH0 QH0 QGn QGn Note: H: High level L: Low level ↑: Low to high transition X: Immaterial a .
.
.
h: Parallel data QA0 .
.
.
Q H0: Outputs remain unchanged.
QAn .
.
.
Q Gn : Data shifted from the previous stage on a positive edge at the clock input.
Pin Arrangement SH/LD 1 CLK 2 E 3 F 4 G 5 H 6 QH 7 GND 8 16 VCC 15 CLK INH 14 D 13 C 12 B 11 A 10 SER 9 QH (Top view) 2 HD74LV165A Absolute Maximum Ratings Item Supply voltage range Input voltage ran...


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